JPH0227884A - Coding mode control system for television signal compression coding device - Google Patents

Abstract

PURPOSE:To eliminate unbalance of the transmission speed of two picture signals by detecting a data quantity stored in a buffer memory by 1st multiplexed picture signal and 2nd multiplexed picture signal respectively and controlling the coding mode of a compression coding circuit independently by the picture signals. CONSTITUTION:The system is provided with a stored data quantity detection circuit 8 detecting the data quantity stored in a buffer memory 5 by two kinds of multiplexed signals, coding mode control circuits 7, 8, and a selection circuit 9. Then the data quantity stored in the buffer memory 5 is detected by the 1st multiplexed picture signal and the 2nd multiplexed picture signal respectively and the coding mode of the compression coding circuit 2 is controlled independently of the picture signals. Thus, the effect of one picture signal onto the other picture signal is avoided and the transmission speed of the two picture signals is balanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a coding mode control method for a television signal compression coding device, and particularly relates to a method for controlling two types of images, a first image signal and a second image signal. The present invention relates to an encoding mode control method when compressing and encoding a multiplexed signal.

[Conventional technology]

Conventionally, for purposes such as television conferencing, two image signals taken from two cameras are converted (multiplexed) into one television signal, as shown in Figures 4 and 5, which are explanatory diagrams. ) to efficiently transmit two image signals using one transmission path. 4 and 5, A, 1, B, B', B' and A1-A4. B and -B4 each indicate an image signal.

When transmitting such a signal via a compression encoding device, encoding parameters have conventionally been controlled using the same method as for general image signals, without taking into account that the signals are multiplexed.

[Problem to be solved by the invention]

As with the conventional compression encoding method described above, when two image signals are not considered, significant information compression is performed using compression encoding techniques such as interframe predictive encoding and variable length encoding. , the randomly generated data is smoothed by a buffer memory and sent to the transmission path,
In the case of a compression encoding device that uses a method that controls the compression encoding mode according to the storage iK of the buffer memory, encoding is performed based on the total information generation amount of the two image signals without distinguishing between the amount of information generated for each of the two image signals. Since the encoding mode is controlled, when the information generation of one image signal is large, the encoding mode of the other image signal is also controlled in the direction of lowering the quality.
There is a problem in that an imbalance occurs in the transmission speed of the two image signals.

Furthermore, in a configuration where several lines are set as block lines and the encoding mode is controlled for each block line, when a large amount of information occurs in the image signal A that is multiplexed in the first half of the image frame, it is multiplexed in the second half of the image frame. The image quality of image signal B deteriorates, and image signal A becomes image signal -DB.
There was an issue of having an impact on

[Means to solve the problem]

The encoding mode control method of the television signal compression encoding device of the present invention multiplexes two types of image signals, a first image signal and a second image signal, in a predetermined line within a television signal frame. A compression encoding means which has a variable length encoding function and compresses and encodes the input PCM image signal, and encodes the encoding mode set in this compression encoding means by converting n (n: integer) lines into one block line. In the compression encoding apparatus, the compression encoding apparatus includes an encoding mode control means for controlling each block line, and a buffer memory for smoothing random data generated by the compression encoding means and sending it to a transmission path. a detection means for detecting the data amount separately for the two types of multiplexed image signals, and a compression encoding mode of the first image signal according to the data amount of the first image signal detected by the detection means; a first encoding mode control means to control, and a second encoding mode to control a compression encoding mode of the second image signal according to the data amount of the second image signal detected by the detection means. and control means.

[Effect]

In the present invention, the amount of data stored in the buffer memory is multiplexed into a first image signal and a second image signal (
B) Detect separately and control the encoding mode of the compression encoding circuit independently for each image signal.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a pulse generation circuit that uses a frame pulse and a clock t-human power, and 2 is a compression encoding circuit that receives a block line signal 1b and a PCM image signal from this pulse generation circuit 1. 2 inputs a PCM image signal in which two types of image signals (image signal A and image signal B) are multiplexed on predetermined lines within a television signal frame, has a variable length encoding function, and performs compression encoding. It constitutes a compression encoding means. 3 is a write address generation circuit which receives the write clock 2a from this compression encoding circuit 2; 4 is a read address generation circuit which receives the buffer memory read clock; and 5 is a buffer memory read address from this read address generation circuit 4. 4a, a pack memory write address 3a from the write address generation circuit 3, and compression encoded data 2b from the compression encoding circuit 2 as inputs. - It is configured to smooth the data and send it to the transmission path.

Reference numeral 6 denotes an accumulated data amount detection circuit, and this accumulated amount detection circuit 6 constitutes a detection means for detecting the amount of data accumulated in the buffer memory 5 on the side of two types of multiplexed image signals. 7.8 is an encoding mode control circuit, 9 is a selection circuit, and these are codes that control the encoding mode set in the compression encoding means for each block line, with n (n: integer) lines being one block line. This constitutes a mode control means. The encoding mode control circuit 7 constitutes an encoding mode control means for controlling the compression encoding mode of the image signal A according to the data amount of the image signal A detected by the detection means, and controls the encoding mode. The circuit 8 constitutes encoding mode control means for controlling the compression encoding mode of the image signal B in accordance with the data amount of the image signal B detected by the detection means.

FIG. 2 is a detailed block diagram showing an embodiment of the accumulated data amount detection circuit 6 in FIG. 1.

In FIG. 2, the same reference numerals as in FIG. 1 indicate corresponding parts, 6-1.6-2 is an AND circuit that receives the image switching signal 1a and clock CK, and 6-3.6-4 is a register. , 6-5 is a selection circuit, 6-6 is a pattern detection circuit, 6
-7.6-8 is a subtraction circuit.

FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2, in which 0) indicates a 7-frame pulse, (b) a PCM image signal, and (C) an image switching signal 1a.
1(d) is the block line signal 1b1(e) is the data storage amount of image signal A 6c, (f) is the data storage amount of image signal B 5a, and (b)) is the encoding mode control signal 9m.

91) shows the amount of data accumulated in the backup memory 6-8a.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained with reference to FIG. 3.

First, the input PCM image signal is supplied to the compression encoding circuit 2 and written into the buffer memory 5 as compression encoding data 2b. The data written in this buffer memory 5 is output to the transmission line as compressed data 5a. and,
Input frame pulse and input clock are generated by pulse generation circuit 1
At the same time, the input clock is supplied to each circuit. The pulse generating circuit 1 outputs an image switching signal 1a and a block line signal 1b. This image switching signal 1a is supplied to a selection circuit 9 and an accumulated data amount detection circuit 6, and a block line signal 1b is supplied to an encoding mode control circuit 7.8 and a compression encoding circuit 2. This compression encoding circuit 2 outputs a write clock 2a synchronized with compressed encoded data 2b to a write address generation circuit 3, and from this write address generation circuit 3, a buffer memory write address 3& is sent to a buffer memory 5 and an accumulated data amount detection circuit. 6.

On the other hand, the buffer memory read clock is supplied to the read address generation circuit 4, and the read address generation circuit 4 supplies the buffer memory read address 4a to the buffer memory 5 and the accumulated data amount detection circuit 6.

Then, from this accumulated data amount detection circuit 6, a buffer memory overflow signal (hereinafter referred to as an overflow signal) 6a1, a buffer memory e underflow signal (hereinafter referred to as an underflow signal) 6b.

Data storage amount 6c of image signal A and data storage amount 6d of image signal B are output, and overflow signal 6a and underflow signal 6b are sent to encoding mode control circuit 7,
The accumulated data amount 6c is supplied to the encoding mode control circuit 7, and the accumulated data amount 6d is supplied to the encoding mode control circuit 8.
are supplied to each.

The encoding mode control circuit T supplies the encoding mode control signal 7a of the image signal A, and the encoding mode control circuit 8 supplies the encoding mode control signal 8a of the image signal B to the selection circuit 9. An encoding mode control signal 9a is supplied from the compression encoding circuit 2 to the compression encoding circuit 2.

Next, in the pulse generating circuit 1, as shown in the time chart of FIG. 3, a PCM image signal (see FIG. 3(b)) is generated from a frame pulse (see FIG. 3(&)) and a clock.
An image switching signal 1a (see FIG. 3(c)) synchronized with the K-multiplexed image signals A and B is generated at a predetermined position, and a block line signal lb (see FIG. 3(c)) indicating the encoding mode switching period is generated. 3 (d)). Then, the encoding mode control circuits 1 and 8 control the data storage amounts 6e and 6d (the third
The encoding mode of the compression encoding circuit 2 is determined and output for each block line based on a predetermined sequence according to the diagram (see Figure (@) l (f)). Furthermore, to prevent the buffer memory 5 from overflowing or underflowing, the encoding mode control circuits 7 and 8 are controlled by an overflow signal 6a and an underflow signal 6b.
The encoding mode is also controlled at the same time.

Then, in the selection circuit 9, the encoding mode control signals 1a and 8a are switched based on the image switching signal 1a, and the encoding mode control signal 9a of each image signal (see FIG.
) is supplied to the compression encoding circuit 2.

Next, the accumulated data amount detection circuit 6 detects the amount of data accumulated in the buffer memory 5 for each of the image signals A and B from the buffer memory write address 3a, the backup memory read address 4a, and the image switching signal 1a. A detailed block diagram of the circuit is shown in FIG.

The subtraction circuit 6-8 shown in FIG. 2 calculates the amount of data stored in the backup memory 5 by subtracting the buffer memory read address 4a from the buffer memory write address 3a. The data storage amount 6-8a of this backup memory is supplied to a subtraction circuit 6-7 and also to a pattern detection circuit 6-6. When the data amount is reached, an overflow signal 6a and an underflow signal 6b are generated. Then, in the subtraction circuit 6-1, the data storage amount 6-5a of the image signal A or image signal B is calculated from the data storage amount 6-8 & of the backup memory.
is subtracted to calculate the data accumulation amount 6-7a of the other image signal.

Data accumulation amount of image signals calculated in this way 6-
18 is supplied to registers 6-3 and 6-4, and clock (CK) supplied from AND circuits 6-1 and 6-2.
), and are outputted as the data storage amount 6C of the image signal A and the data storage amount 6d of the image signal B, and are also supplied to the selection circuit 6-5IC.

Further, when the image signal A is encoded by the image switching signal 1a, the AND circuit 6-2 causes the register 6-4 to
A clock 6-2a is supplied to the encoder, and a change in the amount of data is outputted, and when the data is not encoded, the last amount of data is held because the clock 6-2a is not supplied. Similarly, when image signal B is encoded, clock 6-1 is sent to register 6-3 by AND circuit 6-1.
a is controlled. Further, the image switching signal 1a is supplied to a selection circuit 6-5, which selects the data amount of the unencoded image signal and supplies it to a subtraction circuit 6-7.

In addition, in FIG. 3, the case of multiplexing as shown in FIG. 4 was explained, but when signals are switched and multiplexed for each field as shown in FIG. 5, or multiplexed by other divisions. This can also be easily realized by generating the image switching signal 1a in synchronization with switching of input images.

〔Effect of the invention〕

As explained above, the present invention enables the amount of data stored in the backup memory to be multiplexed into a first image signal and a second image signal.
By detecting the image signal (B) separately and controlling the encoding mode of the compression encoding circuit independently on the image signal side, it is possible to eliminate the influence of one image signal, and
This has the effect of balancing the transmission speeds of the two image signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a detailed block diagram showing an embodiment of the accumulated data amount detection circuit in FIG. 1, and FIG. 3 is a block diagram showing an embodiment of the accumulated data amount detection circuit in FIG. A time chart for explaining the operation, and FIGS. 4 and 5 are explanatory diagrams for explaining the operation. 1...Pulse generation circuit, 2...Compression encoding circuit, 3...Write address generation circuit, 4...Read address generation circuit, 5...Buffer memory,
6. Accumulated data amount detection circuit, T, 8.@-encoding mode control circuit, 9. Selection circuit.

Claims (1)

[Claims] A PCM image signal in which two types of image signals, a first image signal and a second image signal, are multiplexed on a predetermined line is input into a television signal frame, and has a variable length encoding function and is compressed. a compression encoding means for encoding; an encoding mode control means for controlling the encoding mode set in the compression encoding means for each block line, with n (n: an integer) lines as one block line; In a compression encoding device having a buffer memory for smoothing random data generated by a smoothing means and sending it to a transmission path, detection for detecting the amount of data accumulated in the buffer memory for each of the two types of multiplexed image signals. means, first encoding mode control means for controlling the compression encoding mode of the first image signal according to the data amount of the first image signal detected by the detection means, and detection by the detection means. a second encoding mode control means for controlling the compression encoding mode of the second image signal according to the data amount of the second image signal. Encoding mode control method for encoding equipment.