JPH04287587A - Control method for synchronization - Google Patents

Abstract

PURPOSE:To eliminate the need for a card control discrimination circuit and to simplify the circuit constitution by synchronizing the processing of an operation request data of a control section circuit and that of an operation request signal of a coding section circuit. CONSTITUTION:An operation request data outputted from a control section 2 is converted into a request signal of a same form of an operation request signal outputted from a coding section 1 and the input timing and priority with an operation request signal outputted from the coding section 1 are discriminated at a same point of time, the one is selected and a signal to select the operation enabling signal corresponding to the signal is returned to the outputting section. Thus, the operation request data from the section 2 inputted asynchronously is discriminated synchronously with the operation request signal of the section 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization control method for synchronously controlling two asynchronous data systems in an image encoding apparatus. More specifically, the present invention relates to a method for synchronizing data insertion and extraction in an encoding unit and a control unit of an image encoding device.

0002

2. Description of the Related Art In recent years, with the spread of image encoding devices used in TV conference systems and the like, the devices are required to be equipped with various functions. When inserting or extracting data under the control of the control unit, the encoding unit is controlled asynchronously by the control unit, so if the timing of the insertion is not timed, the data may be corrupted midway. Therefore, such control requires synchronization.

FIG. 3 is a block diagram showing the main structure of a conventional image encoding apparatus. The encoding unit circuit and the control unit circuit in the image encoding device each output an operation request signal to the synchronization circuit, and start their respective operations only after receiving an operation permission signal from the synchronization circuit. The synchronization circuit allows the control section circuit to operate based on control signals output from the encoder operation request control circuit 10, the operation determination circuit 11, the operation detection circuit 12 that detects the operation request of the control section circuit, and the operation determination circuit 11. It is composed of an output control circuit 13 that outputs a signal. Note that the numbers shown without using lead lines in the drawings indicate the number of signal lines for each line (the same applies hereinafter).

[0004] The operation request signal from the encoder circuit is input at a fixed timing once every four cycles. This operation request signal is encoded by the encoder 10b via an FF (flip-flop) 10a of the encoder operation request control circuit 10 and output to the operation determination circuit 11. Once the FF 10a latches the operation request signal, it does not latch the next operation request signal for a predetermined period of time. As this encoder 10b,
An 8-3 priority encoder with priority function is used. The encoder 10b converts an octal number into a binary coded octal number, and if two or more data are input at the same time, the largest number is prioritized and output to the operation determination circuit 11 together with an enable output signal.

Separately from this, a control section operation request signal is inputted to the operation detection circuit 12 from the control section circuit. This operation request signal is composed of an address and an address strobe from the CPU in the control section circuit. When the operation request signal is input to the operation detection circuit 12, the operation detection circuit 12 outputs to the operation determination circuit 11 a notification that the operation request signal has been input from the control section circuit to the operation determination circuit 11.

The operation determination circuit 11 compares the input timings of the enable output signal from the encoder 10b of the encoder operation request control circuit 10 and the output signal from the operation detection circuit 12, and determines which one is input first. It recognizes the signal and outputs a control signal indicating output of the operation permission signal to the circuit that outputs the signal. In this case, if the respective output signals are input at the same time, priority is given to the operation request signal output from the encoder circuit.

The circuit that receives the control signal outputs an operation permission signal to the corresponding circuit in accordance with the control signal. That is, in the encoder circuit, the decoder 10c receives the 2 signals from the encoder 10b in accordance with the control signal from the operation determination circuit 11.
The evolved octal number is converted into an octal number and an operation permission signal is outputted via the FF 10d. Further, the output control circuit 13 outputs the signal detected by the motion detection circuit 12 based on the control signal from the motion determination circuit 11 to the control section circuit.

[0008]

[Problems to be Solved by the Invention] In the above method, the operation request signals of the encoder circuit and the control circuit, which are two asynchronous data systems, are recognized by separate circuits. The scale has grown. Furthermore, since the encoder circuit and the control circuit output operation request signals asynchronously, an operation determination circuit is required to monitor and control each operation request signal. This invention has been made in consideration of the above circumstances, and by making the operation request signal from the encoding section and the operation request signal from the control section the same and making a judgment, two asynchronous signals can be synchronously converted. This provides a method for controlling synchronization processing.

[0009]

[Means for Solving the Problems] A synchronization control method of the present invention converts operation request data output from a control section into a request signal in the same format as an operation request signal output from an encoding section, and encodes the operation request data. The input timing and priority of the operation request signal outputted from the conversion unit and the request signal are determined at the same time, and one of the operation request signal and the request signal determined to have been input first is selected. , and when the operation request signal and the request signal are input at the same time, the signal with a higher priority is selected, and the operation permission signal corresponding to the selected signal is output to the section that outputs the selected signal. do.

0010

[Operation] According to the present invention, the operation request data output from the control section is converted into a request signal of the same format as the operation request signal output from the encoding section, and the input of the operation request signal and the request signal is Determines timing and priorities. Therefore, the operation request data inputted asynchronously from the control section can be determined in synchronization with the operation request signal from the encoding section.

[0011]

EXAMPLES Examples of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following examples. FIG. 1 is a block diagram showing the overall configuration for explaining synchronization control in an image encoding apparatus implementing an embodiment of the present invention.

In the configuration shown in the figure, the encoder circuit 1 and the controller circuit 2 each output an operation request signal and operation request data to the synchronization circuit 3, and receive an operation permission signal from the synchronization circuit 3. It is not until later that each operation begins. The encoder circuit 1 includes, for example, a video signal processor "V", which is an LSI manufactured by Fujitsu Ltd.
SP-1” (product name). This LSI performs arithmetic processing on data in units of data. That is, each LSI outputs an operation request signal to the synchronization circuit 3, receives an operation permission signal, reads data from the memory in the memory circuit 3c, and performs arithmetic processing.

Furthermore, the control section circuit 2 uses the CPU to asynchronously directly write/read data to/from the memory in the memory circuit 3c. At the same time, it outputs an address and the like as operation request data, and generates a control signal for writing/reading data from the memory circuit 3c.

As shown in FIG. 1, the synchronization circuit 3 includes an operation request control circuit 3a that determines the operation request signal outputted from the encoder circuit 1 and the operation request data outputted from the control section circuit 2. , an output control circuit 3b that outputs respective operation permission signals in response to signals from the operation request control circuit 3a, and a memory circuit 3c that stores data.

To illustrate this synchronization circuit 3 in more detail, as shown in FIG. A control unit operation request signal generation circuit 4 that generates a signal, and a control unit circuit 2
an output signal generation circuit 5 that generates an operation permission signal for the encoder circuit 1, and determines the priority of the operation request signal from the encoder circuit 1 and the request signal generated by the control section operation request signal generation circuit 4; and an operation determination circuit 6 that outputs an operation permission signal corresponding to one of them.

The operation determination circuit 6 includes an FF (flip-flop) 6 that latches the request signal output from the encoder operation request signal and the control section operation request signal generation circuit 4.
a and encode the signal output from FF6a,
An encoder 6b consisting of an 8-3 priority encoder such as 74148, and a 3-8 priority encoder such as 74138 that decodes the output from encoder 6b.
A decoder 6c consisting of a demultiplexer and a decoder 6
FF6d outputs the signal outputted from C to the encoding unit circuit 1 as an encoding unit operation permission signal. Here, the control section operation request signal generation circuit 4, FF6
a, the encoder 6b and the decoder 6c constitute the operation request control circuit 3a, and the output signal generation circuit 5 and the FF 6c constitute the output control section circuit 3b.

The control unit operation request signal generation circuit is as follows:
A request signal is generated from an address or address strobe that is operation request data output from a CPU built in the control circuit. The request signal is a one-pulse signal having a pulse width corresponding to an address or the like.

Next, the operation of this embodiment will be explained. When the operation request signal is input from the encoder circuit 1 to the operation determination circuit 6, the octal number is input to the encoder 6b via the FF 6a and converted into a binary coded octal number. When the operation request signal is input, the request signal output from the control section operation request signal generation circuit 4 is not taken into the encoder 6b. The binary coded octal operation request signal is decoded by the decoder 6c and outputted as an operation permission signal for the encoder circuit 1 via the FF 6c. in this case,
If two or more bits of the eight bits constituting the operation request signal are input at the same time, the most significant bit is encoded (selected) and output.

Next, when the operation request signal from the encoder circuit 1 and the request signal output from the control section operation request signal generation circuit 4 are input to the encoder 6b at the same time, they are processed according to the preset priority. encoded. This priority setting may be the same as the conventional one, and priority is given to the operation request signal. Therefore, the operation request signal from the encoder circuit 1 and the operation request data from the control section circuit 2 are processed (determined) in synchronization.

When only the request signal from the control section operation request signal generation circuit 4 is latched by the FF 6a and inputted to the encoder 6b, the encoding section circuit The operation request signal from 1 is not input to the encoder 6b. The request signal encoded by the encoder 6b is sent to the decoder 6c.
The signal is decoded by the output signal generation circuit 5 as an operation permission signal for the control section circuit 2, and is output to the control section circuit 2.

As explained above, in this embodiment, the operation request signal from the encoder circuit 1 and the control circuit 2
A single operation determination circuit 6 determines the operation request data from the operation request data.

[0022]

According to the present invention, the processing (control) of the operation request data of the control circuit and the operation request signal of the encoder circuit can be performed simultaneously, that is, in synchronization. Therefore, it is no longer necessary to apply guard control to the operation request signal at the output section or to provide a judgment circuit for this purpose as in the conventional case. This allows the circuit configuration to be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall general configuration of an image encoding device according to the present invention.

FIG. 2 is a block diagram showing the configuration of a synchronization circuit that implements an embodiment of the invention.

FIG. 3 is a block diagram showing the configuration of main parts of an image encoding device to which a conventional example is applied.

[Explanation of symbols]

1 Encoding section circuit 2 Control section circuit 3 Synchronization circuit 4 Control section operation request signal generation circuit 5
Output signal generation circuit 6 Operation determination circuit

Claims (1)

[Claims] 1. Converting the operation request data output from the control section into a request signal having the same format as the operation request signal output from the encoding section, and combining the operation request signal output from the encoding section with the request signal. The input timing and priority of the input signals are determined at the same time, and either the operation request signal or the request signal that is determined to have been input first is selected, and the operation request signal and the request signal are input at the same time. A synchronization control method characterized by selecting a signal with a high priority and outputting an operation permission signal corresponding to the selected signal to a unit that outputs the selected signal.