JPH0537402A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To provide the time division processing type viterbi decoder which reduces the quantity of RAM and is equipped with a path memory circuit using the general purpose RAM of a terminal for both inputting and outputting. CONSTITUTION:RAM 21 and 22 are general purpose RAM equipped with the terminals for both inputting and outputting, are equipped with the N-fold addresses as many as the number of states in a state transition diagram and alternately execute write and read operations according to a write control signal 204 generated by a 1/2 frequency divider 23. According to the signal 204, three-state buffers 54 and 55 control connection between both the RAM 21 and 22 while turning a black mark buffer ON when the RAM 21 is set in a read mode and turning a white mark buffer OFF, for example. When a stricted length K is 3, an encoding ratio R is 1/2 and a cut-off path length is 16, address generators 28 and 29 and selectors 24 and 25 or the like are operated so as to store the information sequence of 16 bits held in the respective states of the state transition diagram while dividing it into 8 bits to the two addresses of the respective RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder for decoding digital information transmitted by a convolutional coding method by a Viterbi decoding method, and more particularly to a path memory circuit in a time division type Viterbi decoder.

[0002]

2. Description of the Related Art In recent years, with the development of digital signal processing technology, various error correction methods capable of correcting code errors occurring in a transmission line have been proposed. The Viterbi decoding method for decoding using the Viterbi algorithm is evaluated as a highly practical decoding technique.

The Viterbi decoder to which the present invention is applied is a time-division processing type. However, in order to facilitate understanding, the constraint length K = 3 and the coding rate R = 1/2 for the Viterbi decoding method are first described.
The case will be described as an example.

The encoder is composed of, for example, a 3-bit (B ₁ , B ₂ , B ₃ ) shift register 40, an exclusive OR circuit 41, 42 as shown in FIG.
1 sequence of binary information signals input from 1 is converted into a 2-symbol codeword sequence according to the state transition diagram shown in FIG.
The signals are output from the output terminals 52 and 53, respectively.

In FIG. 3, the number in the circle of each state S _i ^(j) shows the state of the previous two bits (B ₁ , B ₂ ) of the shift register 40 at the end of the time slot t.
That is, in the state of the previous two bits (B ₁ , B ₂ ), S ₁ ^(j) =
(0, 0), S ₂ ^(j) = (1, 0), S ₃ ^(j) = (0,
1) and S ₄ ^(j) = (1, 1).

Then, for example, from the state S _i ^(j-1) to the state S
_In the transition to _i ^(j) , the transition path P indicated by the solid line with an arrow
Information input bit (1) added above _ii ' ^(j )
Alternatively, when (0) is input from the input terminal 51, the codewords (0, 0) added below the transition path P _ii ′ ^(j ),
It indicates that the respective bits of the same (1, 0), the same (0, 1), and the same (1, 1) are transmitted from the corresponding ones of the output terminals 52, 53.

For example, in the state S ₁ ^(j-1) , (B ₁ , B ₂ )
= (0,0), but when the information bit (0) is input from the input terminal 51 in this state, the information bit (0) is output from both the output terminals 52 and 53, and (B ₁ , B ₂ ) =
The state S ₁ ^{(j) of} (0, 0) is entered. On the other hand, when the information bit (1) is input from the input terminal 51, the output terminal 5
The information bit (1) is output from both 2 and 53 and (B
Transition to state S ₂ ^(j) where ₁ , B ₂ ) = (1, 0).

In the Viterbi decoding method, on the receiving side, the correlation between the received codeword symbol and the expected codeword symbol of the transition path P _ii ′ ^(j) is related to the two paths that join each state in this state transition diagram. (Branch metric)
Each path is added to the cumulative metric in the state before one time slot, and the larger one of them is selected as a path that is more likely (remaining path), and the added value of the remaining paths is set as the cumulative metric of the relevant state. At this time, the operation of adding the information bit corresponding to the path just selected to the information signal sequence that the state of the remaining path one time slot or earlier had, and setting it as the information signal sequence of the state is repeated. This is a method of detecting a unique path and outputting an information signal corresponding to the path as a decoded signal.

As is well known, a general Viterbi decoder is not a time division processing type, but this type of Viterbi decoder has a branch metric generation circuit 11 and an ACS circuit 12 as shown in FIG. And a path memory circuit 13 and a data output circuit 14. FIG. 4 shows the configuration when the constraint length K = 3 and the coding rate R = 1/2.

In FIG. 4, received codeword symbol 101
Is a 2-symbol codeword sequence output from the encoder is received via a transmission system. This is input in parallel to the four correlators arranged in parallel in the branch metric generation circuit 11.

In the four correlators, the transition path P _ii '
^(j) four kinds of expected codeword symbols, that is, (0,
0), (1,0), (0,1), (1,1) corresponding to the input received codeword symbol 101 (branch metric), and the correlation value (branch metric) 102 corresponds to the unit A of the ACS circuit 12
Output to the CS circuit 15.

Since the number of states is 4 when K = 3, the ACS circuit 12 is composed of four unit ACS circuits 15. In each unit ACS circuit 15, the cumulative metric 105 in each state accumulated up to one time slot before and the branch metric 102 in that path are added for the two paths that join the corresponding states of the four states in the state transition diagram. (Add), the results are compared (Compare), and the larger addition value is selected (Select) to obtain the cumulative metric of the state.
At the same time, the selection information is transmitted to the path memory circuit 13 as the path selection signal 103.

The path memory circuit 13 has a pair of a 2-input 1-output selector (S) and a flip-flop (F) arranged horizontally.
It is the one in which the pieces are arranged vertically for the number of states (four pieces). Here, M indicates the length of the path memory, which is called a truncated path length, and the path selection signal 103 sent from the corresponding unit ACS circuit 15 to the M horizontal selectors (S). Is given as a control signal. Then, the vertical four selectors (S) in the input stage have initial values (0, 0), (1,
Corresponding ones of 1), (0, 0), and (1, 1) are set, and signals are input in advance after the second stage.

In the path memory circuit 13, according to the path selection signal 103, an information signal having a length of M bits held by the respective states of the two paths joining the respective states in the state transition diagram before one time slot. One of the sequences is selected and used as a new information signal sequence held by the state. At that time, an information bit corresponding to the selected path is added to the temporally new portion of the information signal sequence, and four vertical flip-flops (F) in the output stage are added.
The data output circuit 14 stores the four time-oldest information bits accumulated in the
Output to.

Although various processing methods are known in the data output circuit 14, for example, an arbitrary one of the 4-bit decoded data candidate bits 106 is selected, or a majority decision is made (0). Alternatively, the decoded data 104 is formed and output by determining (1) or the like.

As described above, the ACS circuit has a configuration in which unit ACS circuits are arranged in parallel for the number of states (four in FIG. 4). In addition, the path memory circuit is a 4M-bit memory circuit in simple terms, but every time a data symbol is input from the demodulator, the memory element of all bits must be rewritten by the plucking operation. General-purpose RA
M or the like cannot be used, and as shown in FIG. 4, four pairs of vertically arranged two-input one-output selectors and flip-flop pairs are arranged side by side. That is, in a general Viterbi decoder, most of the hardware is ACS
Since the circuit and the path memory circuit are occupied, how to reduce the hardware of the ACS circuit and the path memory circuit is the most difficult point for the circuit designer.

Therefore, in order to simplify the circuit, a time-division processing type Viterbi decoder has been proposed. This is based on the following idea. As described above, the ACS circuit has the same number of circuits (unit ACS circuit) as the number of states (4).
However, if the symbol rate is relatively low, the desired ACS circuit processing can be realized by using one unit ACS circuit four times in a time division manner. Then, since the path selection signal is output only one state at a time, the rewriting of each memory element in the path memory circuit is correspondingly performed.
It is sufficient to carry out one state (M bits) at a time.

In this case, the path memory circuit can be constituted by the RAM in which the number of states is assigned to the address and the cutoff path length is assigned to the number of bits. Therefore, the path memory circuit can be simplified similarly to the ACS circuit. However, in this case, it goes without saying that the processing speed of the RAM is required to be four times or more the symbol rate.

Therefore, the path memory circuit of the time-division processing type Viterbi decoder, which is the object of the present invention, has conventionally been constructed as shown in FIG. 5, for example. This path memory circuit includes a pair of (two sides) RAM groups (31, 32).
, 1/2 frequency divider 33, selector (SEL) 34, same 35, same 36, internal clock generator 37, read address generator 38, write address generator 39
And an inverter 40.

The ½ frequency divider 33 divides the externally applied symbol clock 301 by ½ to generate a write control signal 304 which repeats (1) and (0) for each symbol. The write control signal 304 is directly applied to the R / W terminal of one RAM group 31 and controls the R / W terminal of the other RAM group 32 and the selectors (34 to 36) via the inverter 40. It is given to the input terminal.

That is, since the RAM cannot execute "read" and "write" at the same time, two RAM groups are provided, and when one is in the write mode, the other is in the read mode, and these are alternated. There is.

Each of the RAM groups 31 and 32 is formed by arranging a plurality of RAMs in parallel. As described above, the cutoff path length is assigned to the number of input / output bits of the RAM.
For example, when the cutoff path length is R = 1/2, the cutoff path length is 3 to 5 times the constraint length K. However, the number of input / output bits in the available RAM is 8 or 9. Therefore, although the abort path length is arbitrarily set by the designer, the desired abort path length cannot be physically covered by one RAM, and the configuration shown in the figure is obtained. In FIG. 5, the RAM is provided with 8-bit input terminals (I _{0 to} I ₇ ) and 8-bit output terminals (Q _{0 to} Q ₇ ).

The address signal (AD) of the RAM group 31 is given from the selector 34, and the address signal (AD) of the RAM group 32 is given from the selector 35. Between the RAM groups 31 and 32, the least significant bit LSB of the address signal of the write address generator 39 is applied to the first input terminal I ₀ of the frontmost RAM, and the final output terminal (in the illustrated example, The output data bit of the eight output terminals Q ₇ ) is input to the selector 36, while the other input / output terminals are connected so that one output becomes the other input.

The internal clock generator 37 generates an internal clock 305 having a speed equal to or more than the number of states of the symbol clock (4 in the above example), and outputs it to a read address generator 38 and a write address generator 39. Output to.

The outputs (address signals) of the read address generator 38 and the write address generator 39 are input to the selectors 34 and 35, respectively, and the write control signal 3
Controlled by 04, the write address is supplied to the RAM group in the write mode, and the read address is supplied to the RAM group in the read mode.

Here, the write address output from the write address generator 39 is sequentially assigned to the 0 state (0, 0) to the 0 address and the 1 state (1, 0) to the 1 address. .. Further, the read address generator 38 generates a read address under the control of the path selection signal 302 provided from the ACS circuit ⁽ not shown ⁾ , but as is clear from the state transition diagram, in the writing of the state of S _i ^(j) Since the state of S _i ^{(j + 1)} is read, in the case of K = 3, the write mode RAM group outputs 0 address or 2 address to the read mode RAM group when writing 0 state, Similarly, at the time of writing, 0 address or 2 addresses are output, and at writing of 2 states (1, 0) and 3 states (1, 1), 1 address or 3 is output.
Output address.

The latest data in each state to the path memory is input to I ₀ of the RAM, but it can be seen from the state transition diagram that it matches the least significant bit of the write address.

Under the control of the write control signal 304, the selector 36 selects the decoded data candidate bit in each state read from the RAM and the undefined data appearing at the output terminal in the write mode, and time division is performed. The decoded data candidate bit 303 is output.

The 1/2 frequency divider 33, the selectors 34, 35, the internal clock generator 37, the read address generator 38 and the write address generator 39 are usually AC.
The S circuit is also required, and in this case, these are shared by the ACS circuit and the path memory circuit.

[0030]

In the above-mentioned path memory circuit of the conventional time-division processing type Viterbi decoder, the number of input / output bits of the RAM is required to be equal to the length of the cutoff path. As described above, when R = 1/2, the constraint length K is required to be about 3 to 5 times, and the higher the coding rate R is, the more it is required. Therefore, the number of required RAMs increases. ..

For example, if K = 7, then R = 1/2 and about 3
There are 0 bits, about 60 bits at R = 3/4, and about 120 bits at R = 7/8. On the other hand, the number of input / output bits of the RAM is usually 8 or 9. Then, in the conventional path memory circuit, if the number of input / output bits of the RAM is 9, R =
In the case of 7/8, 28 RAMs are required. The fact that 28 Viterbi decoders are required for one RAM is a great disadvantage in terms of space and cost.

Further, in the conventional path memory circuit, the RAM in which the data input terminal and the data output terminal are different terminals, respectively.
However, in view of the terminal function of RAM these days, such a form is rare, and most of them adopt a data input / output terminal. That is, there is also a problem that the conventional path memory circuit lacks versatility.

An object of the present invention is to provide a time-division processing type Viterbi decoder having a small number of RAMs and having a path memory circuit which can be constituted by a general-purpose RAM having a data input / output terminal. To do.

[0034]

In order to achieve the above object, the Viterbi decoder of the present invention has the following configuration. That is, the Viterbi decoder of the present invention is a path memory circuit for storing an information signal sequence corresponding to the remaining path of each transition state of the convolutional code while alternately controlling one of the two-sided RAMs in the write mode and the other in the read mode. In a time-division processing type Viterbi decoder comprising:
In the two-sided RAM, when each input / output terminal also serves as an input / output and the desired truncation path length is divided by the number of input / output bits of the RAM used and rounded up to N, It has an address number N times as many as the number of transition states; and is provided between the RAMs on the two sides and is controlled to switch between a write mode and a read mode to control connection between input / output terminals of both RAMs. A state buffer; and means for generating an address signal for dividing and storing the information signal sequence consisting of the number of bits of the cutoff path length into two addresses.

[0035]

Next, the operation of the Viterbi decoder of the present invention configured as described above will be described. For example, K = 3, R = 1/2,
When the cutoff path length is 16, it is 1 in the conventional RAM.
The 16-bit information sequence held in each state in the state transition diagram is stored in one address, but in the present invention, it is divided into two addresses and stored in 8 bits.
That is, assuming that the number of input / output bits of one RAM to be used is eight, two RAMs for two sides are conventionally required for each, but the present invention only requires one for each.
Further, in the present invention, the RAM uses a terminal for inputting / outputting data using the shared terminal.

Therefore, according to the present invention, the path memory circuit can be constituted by an extremely small amount of general-purpose RAM, and the circuit scale and the cost can be greatly reduced.

By the way, in the present invention, the number of RAM addresses to be used must be twice the number of addresses used in the conventional circuit. However, looking at the development status of RAM, the number of addresses tends to increase. Therefore, increasing the number of RAM addresses is not a limitation in carrying out the present invention.

Further, by having such a structure,
Although the upper limit of the signal speed that can be processed by the Viterbi decoder is lower than that of the conventional circuit, this is also a big issue as the demand for processing low-speed signals is increasing, as in mobile satellite communication systems. There is no limit.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a path memory circuit according to an embodiment of the present invention (when K = 3, R = 1/2, and a cutoff path length = 16).
Indicates. Hereinafter, the part relating to the present invention will be mainly described.

The 1/2 frequency divider 23 has the same configuration as the conventional circuit 33 and generates the write control signal 204 from the symbol clock 201. This write control signal 2
04 is directly given to the R / W terminal of one RAM 21, and the other RAM 2 via the inverter 30.
It is given to the R / W terminal of 2, the control input terminals of the selectors (24 to 26), and the control input terminals of the 3 state buffers (54, 55).

The RAMs 21 and 22 each have an 8-bit terminal (D _{0 to} D ₇ ) that also serves as an input / output and are physically 1
3 state buffers (5
4, 55). That is, the 3-state buffers (54, 55) are controlled by the write control signal 204, and when the RAM 21 is in the read mode, the black-marked buffer is turned on and the white-marked buffer is turned off. On the contrary, when the RAM 22 is in the read mode, the white buffer is turned on and the black buffer is turned off.

Here, the number of addresses of the RAMs 21 and 22 is "8" unlike the conventional circuit. That is, the value 2 obtained by dividing the cutoff path length 16 by the number of input / output bits 8 is multiplied by the number of states 4 to obtain the number 8.

Therefore, the selectors 24 and 25 are functionally similar to the conventional circuit 34 and 35, but the number of input / output bits is different. Since the number of RAM addresses is 8,
The number of bits for two inputs and one output is three.

The internal clock generator 27 has conventionally been 4 times or more as fast as the symbol rate, but in the present invention, it is necessary to generate a clock at N times as fast as the number of states. Here, N is an integer value obtained by dividing the desired truncation path length by the number of input / output bits of the RAM and rounding up, and in this embodiment, N = 2 as described above. Therefore, the internal clock 205 in the present embodiment is a clock having a speed 8 times or more the symbol rate.

The write address generator 29 is a counter that sequentially counts up to N times the number of states in one symbol in accordance with the internal clock 205, and counts from 0 to 7 in one symbol. , Is repeated for each symbol, and a 3-bit address signal indicating each counted value is output to the selectors 24 and 25.

Here, the allocation of RAM addresses is as follows. The information signal sequence held in the 0 state (0, 0) has a new 8 bit temporally at the 0 address (0, 0).
The old part is assigned to 1 address (0, 0, 1) in (0, 0). Similarly, one address (0, 1) has two addresses (0, 1, 0) and three addresses (0, 1, 1), and two addresses (1, 0) has four addresses (1, 0, 0) and 5 addresses (1, 0, 1), 3 states (1, 1), 6 addresses (1, 1, 0) and 7 addresses (1, 1, 1), respectively. Allocate.

On the other hand, the read address generator 28 is controlled by the path selection signal 202, and when the write address is 0 (0, 0, 0), 0 address (0, 0, 0) or 4 address (1, 0, 0), write address is 1
1 address (0, 0, 1) or 5 when (0, 0, 1)
Address (1, 0, 1), write address is 2
When (0, 1, 0), 0 address (0, 0, 0) or 4
Address (1, 0, 0), write address is 3
1 address (0, 0, 1) or 5 when (0, 1, 1)
Address (1, 0, 1), write address is 4
2 addresses (0, 1, 0) or 6 when (1, 0, 0)
The address (1,1,0) is the write address 5
3 addresses (0, 1, 1) or 7 when (1, 0, 1)
The address (1, 1, 1) is the write address 6
2 addresses (0, 1, 0) or 6 when (1, 1, 0)
The address (1,1,0) is the write address 7
3 addresses (0, 1, 1) or 7 for (1, 1, 1)
The addresses (1, 1, 1) are output respectively.

A circuit that outputs such a value can be configured as follows, for example. A counter (counter for counting from 0 to 7) similar to the write address generator 29 is installed, and as the read address to be output, the LSB of the count value is the LSB, the MSB is the second bit, and the path selection signal 202 Is the MSB. At this time, the path selection signal 202 is generated in the ACS circuit so as to "when" 0 "indicates that a state with a smaller number is selected and when" 1 "indicates the opposite". The path selection signal 202
The path selection information for one state in
Since 2 must hold 2 addresses for writing and reading, the ACS circuit needs to operate at half the speed of the internal clock 205.

The selector 26 has the same configuration as the conventional circuit 36 and outputs the information bit read from the RAM. Here, in the RAM, 8 bits of the new part of the information sequence held in a certain state is stored in the even address and the old 8 bits are stored in the odd address, so that the selector 26 has the write address of the odd number. The time-division decoded data candidate bit 203 is sometimes output, but when it is even, the information bit to be written to the next address is output.
Therefore, in order to hold this "information bit to be written at the next address" for one clock, the flip-flop 18
Is installed. The output of the flip-flop 18 is one input of the selector 19.

In the selector 19, the second bit (second bit) of the write address signal is applied to the other input, and the least significant bit LSB of the write address signal is used as a control signal, and one of the two inputs is used as the first bit of the RAM. 1 Output to the input terminal I ₀ . As a result, the latest information bit in each state is written in the first input terminal I ₀ of the RAM at the even address, and the information bit held in the flip-flop 18 is written at the odd address.

[0051]

As described above, according to the time-division processing type Viterbi decoder of the present invention, the path memory circuit can be constituted by an extremely small amount of general-purpose RAM, so that the circuit scale and the cost can be greatly reduced. effective.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an example of a path memory circuit used in a time-division processing type Viterbi decoder of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an encoder.

FIG. 3 is a state transition diagram of the encoder shown in FIG.

FIG. 4 is a general configuration block diagram of a Viterbi decoder that is not a time division processing type.

FIG. 5 is a configuration block diagram showing an example of a conventional path memory circuit used in a time-division processing type Viterbi decoder.

[Explanation of symbols]

 18 Flip-flop 19 Selector 21 RAM 22 RAM 23 1/2 divider 24 Selector 25 Selector 26 Selector 27 Internal clock generator 28 Read address generator 29 Write address generator 30 Inverter 54 3 State buffer 55 3 State Buffer 201 Symbol clock 202 Path selection signal 203 Time division decoded data candidate bits 204 Write control signal 205 Internal clock

Claims (1)

Claim: What is claimed is: 1. A path memory for storing an information signal sequence corresponding to a remaining path in each transition state of a convolutional code while alternately controlling one of two-sided RAMs in a write mode and the other in a read mode. In a time-division processing type Viterbi decoder including a circuit; the path memory circuit includes the two-sided RAM.
However, each input / output terminal is also used for input / output,
When the desired truncation path length is divided by the number of input / output bits of the RAM to be used and rounded up to N,
And a RAM having N times as many addresses as the number of transition states; and provided between the RAMs on the two sides and controlled to switch between a write mode and a read mode.
A 3-state buffer for controlling the connection between the input and output terminals, and means for generating an address signal for dividing and storing the information signal sequence consisting of the number of bits of the truncated path length into two addresses. Viterbi decoder characterized by.