JP3288262B2 - Data interleave circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data interleaving circuit for changing the order of data transmission on a transmission side and transmitting the data in order to disperse errors on the reception side in wireless communication and the like, and in particular, to reduce the power consumption thereof It is about the conversion.

[0002]

2. Description of the Related Art Code Division Multiple Access
In wireless communication such as iple Access (hereinafter referred to as “CDMA”), a data to be transmitted is converted into a code sequence called symbol data by using a convolutional encoder, and the symbol data is transmitted by a radio signal. I have. On the receiving side, on the other hand, after demodulating the received radio signal into symbol data, the decoder reproduces the original data from the symbol data. In the decoding process by this decoder, errors occurring on the transmission path are corrected, so that the original data is correctly reproduced. In mobile phones and the like, different degrees of significance are given depending on data. That is, a low significance is given when there is no sound or a busy call, and a high significance is given when there is a free line. Then, according to this significance, the original data rate is 1200, 2400, 480.
It is set to one of four types of 0.9600 bps. On the other hand, the speed of the symbol data to be transmitted needs to maintain a constant transmission speed regardless of the original data speed. For this reason, when the original data rate is low and the number of transmission symbol data is small, the same symbol data is repeatedly transmitted several times in accordance with the data rate to keep the transmission rate constant.

In the case of wireless communication such as the CDMA communication system, there is a high possibility that a communication error such as a data block loss due to fading or the like will occur. When all the transmission data for a certain period of continuous data is lost, it is impossible to estimate and correct the missing part and restore the original data state only by the ordinary convolutional code and its decoding. For this reason, a method called interleaving, in which the transmission order of data to be transmitted after convolutional coding is rearranged at a relatively long period on the transmission side, is often used. Then, the symbol data is transmitted after the continuity of the symbol data, that is, the continuity of the original data is eliminated by this interleaving. Conventionally, a circuit for repeating symbol data and a circuit for interleaving are configured as separate circuit blocks. A circuit for repeating symbol data uses a memory for temporarily storing symbol data, performs an operation of repeatedly writing the same symbol data as many times as necessary to this memory, and simultaneously inputs a plurality of symbol data at a time. Therefore, the writing position is selected using a selector or the like.
In the interleaving circuit, the symbol data sequence is rearranged by sequentially reading out the symbol data written in the temporary storage memory in accordance with a predetermined rule for rearranging the symbol data for each original data rate. The operation is performed and output as transmission information.

[0004]

However, the conventional circuit for repeating symbol data and the circuit for performing interleaving have the following problems. In a circuit that repeats symbol data, it is necessary to perform the same number of times of writing the symbol data to the memory whether the data is low-speed data having a small absolute number of symbol data or high-speed data having a large absolute number of symbol data. Yes, the number of circuit operations is constant regardless of the data speed. For this reason, in the case of low-speed data, although the number of symbol data is small and the number of times of writing is small, the power consumption of the circuit cannot be reduced. Further, a selection circuit such as a selector is required for selecting a writing position,
This leads to an increase in circuit scale and power consumption. In addition, in a circuit that performs interleaving, it is necessary to read the stored data by changing the address every time the address of the memory in which the symbol data is stored changes according to the data reading order. For this reason, regardless of the data speed, it is necessary to read out all the data stored in the memory and perform the rearrangement, and the power consumption of the circuit cannot be reduced. The present invention solves the problem of the prior art, integrates a circuit for repeating symbol data and a circuit for interleaving, and writes and reads symbol data a number of times corresponding to the data rate. And a data interleaving circuit capable of reducing power consumption.

[0005]

According to a first aspect of the present invention, in a data interleaving circuit, M (where M is plural) in a first cycle corresponding to a data rate. Bit-by-bit input data is sequentially provided, and the provided input data is sequentially shifted and held in M-bit units, and the held input data is output in parallel (where N is a plurality). Means, reading means for reading the input data held in the N-stage holding means as M × N-bit parallel data in a second cycle corresponding to the data rate, and reading the read parallel data, Selecting means for sequentially selecting in a fixed order different from the input order and outputting the data as serial data in a third cycle according to the data rate.

According to a second invention, a holding means according to the first invention is provided.
A memory having M × N bits per word and having an input terminal and an output terminal for each bit is provided with the M-bit input data to the first to M-th input terminals, The parallel data from the first to M × (N−1) th output terminals are respectively supplied to the (M + 1) th to (M × N) th input terminals, so that the given input data is in M-bit units. Are sequentially shifted and held. According to the present invention, since the data interleave circuit is configured as described above, the following operation is performed. When the input data in the unit of M bits is sequentially supplied in the first cycle, the data is shifted in the unit of M bits by the holding unit, and the data of M × N bits is held. This M ×
The N-bit data is read as parallel data by the reading means. Furthermore, the selection unit selects an order different from the order input in a cycle corresponding to the data rate and outputs the serial data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of a data interleave circuit showing a first embodiment of the present invention. The data interleave circuit 10 is incorporated in a wireless terminal such as a mobile phone, for example, and has a write control unit 11 to which the symbol data SYM from the convolutional encoder 1 is given.
For example, in the case of a wireless terminal having an encoding rate R = 1/3, the convolutional encoder 1 encodes the transmission data SD and converts the 1-bit transmission data SD by the constraint length of the convolutional encoder 1. Symbol data SY of three affected symbols
M is generated and output to the write control unit 11. Also, the convolutional encoder 1 performs convolutional encoding at a processing cycle of one frame unit.
The maximum number of data in one frame is, for example, 192 bits. Therefore, the symbol data SYM output from the convolutional encoder 1 has 576 symbols per frame.

Normally, even if the speed of input transmission data SD is slow and the number of data in one frame unit is 192 bits or less, the number of symbols in one frame is always 576 symbols by repeating the processing. Will do. The write control unit 11 performs a process of sequentially writing the symbol data SYM given from the convolutional encoder 1 to a holding unit (for example, a memory) 12 connected to the output side. The write controller 11 stores the original data rate (for example, 1200, 2400, 4800, or 96) of the symbol data SYM to be written from the outside.
A data rate instruction signal SPD indicating the data rate instruction is given, and the amount of data to be written is controlled based on the data rate instruction signal SPD. The memory 12 temporarily stores the symbol data SYM provided from the write control unit 11 to the input terminal DI.
According to the temporarily stored symbol data SYM, 192
It has a storage capacity of bits × 3 words. That is, the memory 12 is set to have a storage capacity capable of writing all the symbol data SYM for one frame by changing the address signal ADR applied to the address terminal AD three times. Address terminal A of memory 12
D is an address control unit 13, and an output terminal DO is a readout unit and a selection unit (for example, a readout selection unit) 20.
Are connected respectively.

The address control unit 13 controls writing and reading addresses to and from the memory 12. To manage addresses of up to three words in the memory 12, a 2-bit address counter 1 for writing is used.
3a and a 2-bit address counter 1 for reading
3b. The read selection unit 20 has a function of reading data from the memory 12 based on the data rate instruction signal SPD according to a read rule specified for each data rate and outputting the data as transmission information OUT. . FIG. 2 shows an input terminal D of the memory 12 in FIG.
FIG. 4 is a connection diagram illustrating a connection relationship between I and an output terminal DO. The memory 12 has 192 input terminals DI ₀ , DI ₁ ,.
I ₁₉₁ , and also 192 output terminals DO ₀ , D
O ₁ ,..., DO ₁₉₁ . And the memory 12
The write control unit 1 is connected to three input terminals DI _{0 to} DI _2.
One to three symbol data SYM are given.
Furthermore, input terminals DI _{3i to} DI _{3i + 2} (where i = 1 to 6
3) are supplied with output signals from output terminals DO _{3i-3 to} DO _3i-1 respectively. The output terminals DO _{0 to} DO ₁₉₁ are connected in parallel to the 192 input sides of the read selection unit 20. Thus, the memory 12 is connected so as to form a shift register.

FIG. 3 is a configuration diagram of the read selection unit 20 in FIG. The read selection unit 20 determines the seventh bit from the least significant bit (hereinafter referred to as “LSB”) of the output signals output from the output terminals DO _{0 to} DO ₁₉₁ of the memory 12.
There are eighteen four-input selectors 21 _{1 to} 21 ₁₈ for dividing up to the second bit into four lines and selecting one of them. Further, from the 73 th bit of the output signal of the memory 12 until the 144 th bit is separated one by eight, is connected to the input side of the nine 8-input selector 22 _{1-22 9} I have. Furthermore, the 145-th most significant bits from the bits of the output signal of the memory 12 (hereinafter, referred to as "MSB") up, separated into individual 16, three 16-input selector 23 21 _to
It is connected to the 3 ₃ on the input side. 18 selectors 21
Output of ₁ to 21 ₁₈ is output as 1200bps output signal, is connected to the input side of the separated one by two and nine 2-input selector 24 _{1-24 9.}
The selector 24 _{1-24 9,} and selector 22 _{1-22 9}
Is output as a 2400 bps output signal and is divided into two and connected to the input sides of _nine 2-input selectors 25 _{1 to} 25 ₉ . Selector 2
5 _to 253 _9, and selector 23 _{1-23 3} on the output side is output as 4800bps output signal of six separated by a two by two 2-input selector 26 ₁
26C is connected to the ₆ input of. Then, the output of the selector 26 ₁ to 26 _6, so that the 9600bps output signal is output.

[0011] Further, the 1200 bps output signal is divided into three signals, each of which has six three-input selectors 27 _j (where j =
1 to 6). The 2400 bps output signal is divided into three units and connected to the input side of six three-input selectors _28j . The 4800 bps output signal is divided into two, each of which has six 2-input selectors 2.
9 _j is connected to the input side. These selectors 27
The output sides of _j , 28 _j and 29 _j and the 9600 bps output signal are respectively connected to the input side of a 4-input selector 30 _j , so that the transmission information OUT is output to the output side of the selector 30 _j . . Next, the operation will be described.

In the case of 9600 bps, 192 bits (5
Since the convolutional encoder 1 shown in FIG. 1 outputs three symbol data SYM at a time, the write control unit 1
In step 1, as shown in FIG. 2, write processing is sequentially performed on the memory 12 for every three symbols. By performing the writing operation 64 times, the symbol data S of 192 symbols can be obtained.
The YM is written to the memory 12, and the write address counter 13a in the address control unit 13 is updated once. The symbol data SYM in the memory 12 is shifted to the upper digit in units of 3 bits and written again to the memory 12, so that when 64 write operations are completed, 1
This means that all data of the word (192 bits) has been written. Then, the address counter 13a is updated, writing to the next address is performed, and writing of 576 symbols is completed when writing to all three words is completed. In the case of 4800 bps, since the data amount is 96 bits (288 symbols), the address is updated once after the writing of 192 symbols of data is completed in 64 writings as in the case of 9600 bps, and the next address is used. The remaining 96 symbol data is similarly stored in the designated memory location in units of 3 symbols.
Write twice. In the case of 4800 bps, the address of the memory 12 has been updated only once.

In the case of 2400 bps, the data amount is 4
Since it is 8 bits (144 symbols), the writing of data of all symbols is completed by writing 48 times for every three symbol data, and the address is not updated. In the case of 1200 bps, the data amount is 2
Since it is 4 bits (72 symbols), writing of data of all the symbols is completed by writing 24 times for every three symbol data, and the address is not updated as in the case of 2400 bps. . Thus, the symbol data SYM from the convolutional encoder 1 is
Represents the symbol data S corresponding to the data rate without repeatedly writing the same symbol data SYM multiple times.
Writing the YM to the memory 12 only once completes the writing process.

When the process of writing all the symbol data SYM for one frame output from the convolutional encoder 1 to the memory 12 is completed, the readout selecting section 20 outputs the data based on the data rate instruction signal SPD given from the outside.
The reading order of the symbol data SYM from the memory 12 is selected, and the selection and output of the symbol data SYM are sequentially performed. In the case of the terminal of the CDMA communication system, which is the slowest data rate of 1200 bps, the symbol data SYM written in the memory 12 is, as shown in FIG.
B is read out every 4 bits. When the data rate is 2400 bps, data is read out every 8 bits, when the data rate is 4800 bps, data is read out every 16 bits, and when the data rate is 9600 bps, data is read out every 32 bits. In the case of 1200 bps, a total of 72 pieces of symbol data SYM are
The selection signals of the selectors 21 _{1 to} 21 ₁₈ and 27 _j are set to 0 selection to perform reading. At this time, the six symbol data SYM can be read at the same time, and the first, fifth, ninth, thirteenth, seventeenth, and twenty- _first symbol data SYM can be taken out by the first reading, and then the selector 21 ₁
To 21 ₁₈ of the selection signal only selection signal of the selector 27 _j without operating by operating from 0 to 1, followed by 2
The fifth, 29, 33, 37, 41, and 45th symbol data SYM can be read.

Furthermore, only the selection signal of the selector 27 _j 1
By updating from 1 to 2 times, 49, 5
The third, 57, 61, 65, and 69th data can be read. After this operation is repeated eight times, the selection signals of the selectors 21 _{1 to} 21 ₁₈ are updated once and set to select 0 to 1, and the selector 27 _j is set to select 0 again. By performing reading, the following 2,
The sixth, tenth, fourteenth, eighteenth, and twenty-second data can be read. After sequentially updated every reading a selection signal of the selector 27 _j, updated once a selection signal of the selector 21 ₁ to 21 ₁₈ after repeating operation eight times to read by selecting 2, similarly selector 27 The control and update of _j are repeatedly performed together with the reading of the symbol data SYM.
When the selection signal of the selectors 21 _{1 to} 21 ₁₈ selects 3, and the selection signal of the selector 27 _j repeats the cycle from 0 to 2 eight times, the reading is completed and 9 is set every 6 bits.
Six reading {3 (number of operations of the selector 27 _j) × 8
Performed (number of repetitions) × 4 (the number of operations of the selectors ₂₁ 1 to 21 _18)}, so that reading the 576 symbols.

In the case of such a read operation, the memory 1
Since the number of bits per word of 2 is 192 bits, it is not necessary to update the address of the memory 12.
For this reason, only a part of the selectors 21 and 27 for selection operate and the 6-bit symbol data SYM
Is obtained, the number of operations of the read selection unit 20 can be reduced to 1/6. Also, the data rate is 4800 bps
In the above case, it is necessary to change the address of the memory 12, but also in this case, the frequency at which the address signal ADR and the selectors 21, 22, 29, etc. must be operated at the same time is extremely reduced. Further, the read selection unit 2
Since the number of operations of 0 is 1/6, the rate of simultaneous operation of the circuits is reduced, and power consumption can be reduced. As described above, in the first embodiment, the following (1) to (3)
There are advantages such as:

(1) When writing the symbol data SYM from the convolutional encoder 1 to the memory 12, the memory 12 connected so as to form a shift register is used. And the circuit scale and power consumption can be reduced. (2) Since the writing of the symbol data SYM to the memory 12 can be performed only once without depending on the original data rate, the operation rate of the circuit can be reduced, and the power consumption of the circuit can be reduced. Further, since it becomes unnecessary to write the same symbol data SYM a plurality of times, it is not necessary to repeatedly write the same symbol data SYM at a high speed, so that a high-speed clock signal is not required and power consumption can be reduced. (3) The read selection unit 20 pays attention to the regularity of the interleaving, and determines the relationship between the bits and the words in the memory 12 by 19
In addition to the 2-bit × 3-word configuration, the configuration of the selection circuit such as the selector 21 for reading is set to a multiple of four. This makes it possible to reduce the number of operations of the memory 12 and the number of operations of the selection circuit.
The bit symbol data SYM can be read from the memory 12. By reducing the number of operations of the read selection unit 20 to one sixth, the power consumption of the circuit can be reduced.

Second Embodiment FIG. 4 is a configuration diagram of a data interleave circuit showing a second embodiment of the present invention. The data interleave circuit 40 is incorporated in, for example, a transmitter on the radio base station side of a mobile phone system, and is provided with a write control unit 41 to which symbol data SYM from the convolutional encoder 2 having a coding rate R = 1/2 is given. have. The write control unit 41 is provided with two-symbol symbol data SYM affected by the constrained length of the convolutional encoder 2 for one-bit transmission data SD. Also, the convolutional encoder 2
Corresponding to the maximum data number of 192 bits per frame, 384 symbols of symbol data SYM are always given per frame. The write control unit 41 converts the symbol data SYM given from the convolutional encoder 2 into a memory 42 connected to its output side.
Is sequentially written. The write controller 41 controls the amount of data to be written based on the data speed instruction signal SPD.

The memory 42 temporarily stores the symbol data SYM provided to the input terminal DI from the write control section 41, and temporarily stores the symbol data SYM.
Has a storage capacity of 192 bits × 2 words. That is, the memory 42 is set to have a storage capacity capable of writing all the symbol data SYM for one frame by changing the address signal ADR applied to the address terminal AD twice. The address control unit 43 is connected to the address terminal AD of the memory 42, and the read selection unit 50 is connected to the output terminal DO. The address control unit 43 controls writing and reading addresses to and from the memory 42. In order to manage 2-word addresses of the memory 42, 1-bit address counters 43a and 43b for writing and reading are used. have. The read selection unit 50 has a function of reading data from the memory 42 based on the data rate instruction signal SPD according to a read rule specified for each data rate and outputting the data as transmission information OUT. .

FIG. 5 shows an input terminal D of the memory 42 shown in FIG.
FIG. 4 is a connection diagram illustrating a connection relationship between I and an output terminal DO. The memory 42 has 192 input terminals DI ₀ , DI ₁ ,.
I ₁₉₁ , and 192 output terminals DO ₀ , DO ₁ ,.
DO ₁₉₁ . Then, two symbol data SYM are given from the write control unit 41 to two input terminals DI _{0 to} DI ₁ of the memory 42. Further, output signals from output terminals DO _{2k-2 to} DO _2k-1 are given to input terminals DI _{2k to} DI _{2k + 1} (where k = ₁ to 95). Also, the output terminals DO _{0 to} D ₀
O ₁₉₁ is connected in parallel to the 192 inputs of the read selection unit 50. Thus, the memory 42 is connected so as to form a shift register. FIG. 6 is a configuration diagram of the read selection unit 50 in FIG. The read selection unit 50 outputs the output terminals DO _{0 to} DO
_From the LSB of the output signal output from
There are eighteen eight-input selectors 51 _{1 to} 51 ₁₈ for dividing the up to the fourth bit into eight lines and selecting one of them. Further, from the 145 th bit of the output signal of the memory 42 until the 288 th bit is separated one by 16, is connected to the input side of the nine 16-input selectors 52 ₁ to 52 ₉ I have. Further, the portion from the 289th bit to the MSB of the output signal of the memory 42 is divided into 32 lines, and three 3 bits are output.
It is connected to the input side of two input selectors 53 _{1 to} 53 ₃ .

The output sides of the _eighteen selectors 51 _{1 to} 51 ₁₈ are output as 1200 bps output signals and are divided into two parts each of nine nine-input selectors 54 _1.
It is connected to the input side of the to 54 _9. Selectors 54 _1-
54 _9, and the output of the selector 52 ₁ to 52 _9, 24
Is outputted as the 00bps output signal, is connected to the input side of the 9 is divided into two by two two-input selectors 551 _to 554 _9. The output sides of the selectors 55 _{1 to} 55 ₉ and the selectors 53 _{1 to} 53 ₃ are 4800 bps.
Is outputted as an output signal, is connected to the input side of the 2 separated by six to two by two-input selector 56 _{1-56 6.} Then, the output of the selector 56 ₁ to 56 _6, so that the 9600bps output signal is output. Further, the 1200 bps output signal is divided into three lines, and each of the six three-input selectors 57 _l (where l = 1 to 1)
6) is connected to the input side. The 2400 bps output signal is divided into three signals, each of which has six three-input selectors 58.
₁ is connected to the input side. The 4800 bps output signal is divided into two lines, each of which has six 2-input selectors _59l.
Is connected to the input side. These selectors 57 _l ,
The output sides of 58 _l and 59 _l and the 9600 bps output signal are respectively connected to the input side of a four-input selector 60 _{l so} that transmission information OUT is output to the output side of the selector 60 _l .

Next, the operation will be described. When two pieces of symbol data SYM are output at a time from the convolutional encoder 2 in FIG. 4, the write control unit 41 performs, as shown in FIG.
The writing process is sequentially performed on the memory 42 every two symbols. By performing the write operation 96 times, the symbol data SYM of 192 symbols is written to the memory 42, and the write address counter 43a in the address control unit 43 is updated once. Since the symbol data SYM in the memory 42 is shifted to the upper digit in units of 2 bits and written again to the memory 42, all the data for one word (192 bits) is written when 96 write operations are completed. It will be. Then, the address counter 43a is updated, and writing to the next address is started. In this manner, the symbol data SYM from the convolutional encoder 2 is stored in the memory 4 only once without repeating the same symbol data SYM multiple times and writing the symbol data SYM in accordance with the data rate.
Writing to 2 completes the writing process.

When the process of writing all the symbol data SYM for one frame output from the convolutional encoder 2 to the memory 42 is completed, the read selecting section 50 stores the symbol data SYM in the memory based on the data rate instruction signal SPD given from the outside. The reading order of the symbol data SYM from the symbol data SYM is selected, and the symbol data SYM is selected and output sequentially. In the case of a wireless base station of the CDMA communication system, in which the data rate is 1200 bps, the symbol data SYM written in the memory 42 is read from the MSB every 8 bits as shown in FIG. Also, every 16 bits when the data rate is 2400 bps, every 32 bits when the data rate is 4800 bps,
When the data rate is 9600 bps, data is read out every 64 bits. For example, if the data rate is 12
In the case of 00 bps, a total of 48 symbol data SY
M is repeatedly read eight times from the MSB of the memory 12 every eight bits in the following order.

1, 9, 17, 25, 33, 41, 5, 1
3, 21, 29, 37, 45, 3, 11, 19, 27,
35, 43, 7, 15, 23, 31, 39, 47, 2,
10, 18, 26, 34, 42, 6, 14, 22, 3
0, 38, 46, 4, 12, 20, 28, 36, 44,
8, 16, 24, 32, 40, 48 In the case of such a read operation, since the number of bits per word of the memory 42 is 192 bits, it is not necessary to update the address of the memory 42. For this reason, 6-bit symbol data SYM can be obtained at a time only by operating only a part of the selectors 51 and 52 for selection, and the number of operations of the readout selection unit 50 can be reduced to one sixth. Except for the case where the data rate is 9600 bps, there is no need to update the address of the memory 42,
The read operation in accordance with the interleave rule can be performed only by operating the selector 51 and the like.

When the data rate is 9600 bps,
Although it is necessary to change the address of the memory 42, even in this case, the frequency at which both the address signal ADR and the selectors 51, 52 and the like must be simultaneously operated is extremely reduced. Further, the number of operations of the read selection unit 50 is 6
Since it is one-half, the rate of simultaneous operation of the circuit is reduced,
Power consumption can be reduced. As described above, the data interleave circuit 40 of the second embodiment has the same advantages as the data interleave circuit 10 of the first embodiment.
Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e).

(A) The data rate is 1200 to 9600
The present invention is not limited to bps, but can be applied to any data rate according to the application. (B) The frame length is not limited to 192 bits, and can be applied to any frame length according to the application. In that case, the storage capacity of the memories 12, 42 is
What is necessary is just to set the capacity according to the frame length. (C) The coding rate R is not limited to 1/2 and 1/3,
It can be applied to any coding rate according to the application. (D) For temporary storage of symbol data SYM, memories 12 and 42 connected to form a shift register
But the symbol data S that needs to be stored
When the amount of YM is small, a similar function can be realized by using an element such as a flip-flop or a latch. (E) The memory 42 according to the second embodiment has 192
Although it has a structure of 2 bits × 2 words, if it is not necessary to read 6-bit data at a time by the CDMA method, the bit direction of the memory 42 is changed to 16 bits which is the minimum number of interleave data reading intervals. The same function can be realized by setting the multiple and increasing the word direction by that amount.

[0027]

As described in detail above, according to the first aspect, the present invention has the holding means for shifting and holding the input data in units of M bits, and the M × S output in parallel.
There is a selecting means for selecting and outputting the N-bit data in an order different from the input order. Thus, even when the input is low-speed data, high-speed output data can be obtained by one write operation, so that the rate of simultaneous operation of the circuit is reduced, and power consumption can be reduced. According to the second aspect of the present invention, since a memory is used as the holding means and the connection is made so as to constitute a shift register, the holding means having a large capacity can be easily obtained, and the circuit scale is reduced and the power consumption is reduced. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data interleave circuit according to a first embodiment of the present invention.

FIG. 2 is a connection diagram showing a connection relationship between an input terminal DI and an output terminal DO of a memory 12 in FIG.

FIG. 3 is a configuration diagram of a read selection unit 20 in FIG. 1;

FIG. 4 is a configuration diagram of a data interleave circuit according to a second embodiment of the present invention.

5 is a connection diagram showing a connection relationship between an input terminal DI and an output terminal DO of a memory 42 in FIG.

FIG. 6 is a configuration diagram of a read selection unit 50 in FIG. 4;

[Explanation of symbols]

 10, 40 data interleave circuit 11, 41 write control unit 12, 42 memory 13, 43 address control unit 20, 50 read selection unit

Claims (2)

(57) [Claims] 1. Input data in M (where M is a plurality) bit units are sequentially provided in a first cycle according to a data rate, and the provided input data is sequentially shifted and held in M bit units. And N (where N is a plurality) stages of holding means for outputting the held input data in parallel, and the input data held in the N-stage holding means is stored in a second cycle corresponding to the data rate. Reading means for reading the data as M × N-bit parallel data, and sequentially selecting the read parallel data in a fixed order different from the input order, and serially selecting the read data in a third cycle according to the data rate. A data interleaving circuit, comprising: selection means for outputting the data as data. 2. The memory according to claim 1, wherein said holding means is M × N per word.
Using a memory having bits and having an input terminal and an output terminal for each bit, the first to Mth input terminals are supplied with the M-bit input data, and the M +
The first to M × N input terminals are connected to the first to M × N (N−
2. The data according to claim 1, wherein the parallel data is supplied from the output terminal in (1), and the supplied input data is sequentially shifted and held in M-bit units. Interleave circuit.