JP3257051B2 - Interleave circuit and de-interleave circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave circuit and a deinterleave circuit suitable for application to, for example, a mobile communication system.

[0002]

2. Description of the Related Art In a mobile communication system such as a car telephone system, there is a communication system in which digital data transmission is performed between a base station and a mobile unit (terminal station). FIG. 14 is a diagram showing an example of a mobile phone configured as a terminal station in this case. In the figure, reference numeral 1 denotes an antenna, which receives a signal transmitted from a base station and supplies the signal to a receiving circuit 2. The signal of a predetermined channel is demodulated by the receiving circuit 2 and supplied to the channel decoder 10. The channel decoder 10 performs a decoding process, which will be described later, which is determined by the communication method, supplies the processed data to the audio codec circuit 3, and converts the data into an analog audio signal. Then, the converted analog voice signal is transmitted to the handset 4
Is output from the speaker 5 connected to. In this case, the receiving channel in the receiving circuit 2 is the frequency synthesizer 8
Is determined by the output frequency signal. The output frequency of the frequency synthesizer 8 is controlled by the control circuit 30.

[0003] As a configuration of a transmission system, an audio signal picked up by a microphone 6 connected to a handset 4 is supplied to an audio codec circuit 3 and converted into a digital audio signal. Then, the converted digital audio signal is supplied to the channel encoder 20, an encoding process which will be described later is determined according to the communication method, and the processed data is supplied to the transmission circuit 7, where the data is modulated into a signal of a predetermined channel, and the signal is transmitted to the antenna. 1 is transmitted. In this case, the transmission channel in the transmission circuit 7 is determined by the frequency signal output from the frequency synthesizer 8.

The control circuit 30 includes a dial key 3
1 and the display panel 32 are connected, and the dial key 3
The transmission processing based on the operation 1 is performed under the control of the control circuit 30. The display panel 32 displays dial numbers and the like under the control of the control circuit 30. Further, the control circuit 30 performs control based on control data transmitted from the base station.
Each circuit is controlled.

[0005] Here, the decoding processing in the channel decoder 10 and the encoding processing in the channel encoder 20 are processed in the configuration shown in FIG. That is,
As a decoding process in the receiving system, after the received data output from the receiving circuit 2 is descrambled by the decryption circuit 11, the burst data as the received data is supplied to the de-interleave circuit 12. Then, the de-interleave circuit 12
Deinterleave the interleaved and transmitted digital data to restore the original block data. This restoration process is performed by a process using a RAM memory. Then, the block data is supplied to the Viterbi decoder 13 to decode the convolutionally encoded data on the transmission side. Then, it supplies the decoded source data to the parity checker 14, performs error correction processing by parity check, and supplies the processed data to the audio codec circuit 3 side.

As an encoding process in the transmission system, the transmission source data output from the audio codec circuit 3 is supplied to the parity generation circuit 21 to add an error correction parity. Then, the source data to which the parity has been added is supplied to the convolutional encoder 22 to be convolutionally encoded block data. Then, the block data is supplied to an interleave circuit 23 to be interleaved burst data. This interleaving process is also performed by a process using a RAM memory, like the de-interleaving process. Then, the interleaved burst data is transferred to the encryption circuit 2.
4 for scrambling, and the scrambled burst data is supplied to a transmission circuit 7 for transmission on a predetermined channel. These decoding processing and encoding processing are performed under the control of the control circuit 30.

Next, interleave processing and de-interleave processing using a memory will be described. For example, the interleave processing is performed by an interleave circuit shown in FIG. That is, the convolutionally coded block data obtained at the terminal 41 is supplied to the memory 42,
Once. The memory 42 is composed of a RAM having a capacity capable of storing two blocks of data, and is divided into a memory a and a memory b for each storage capacity of one block.
By changing the order of writing and reading data to and from the memory 42, interleaved burst data is obtained at the terminal 43.

As control of the interleave processing in the memory 42, start signals a and b are supplied from the control circuit 30 to terminals 44 and 45, and the start signal a obtained at the terminal 44 is counted by a counter 46. The start signal b obtained at the terminal 45 is counted by the counter 47. Then, the count output of the counter 46 is supplied to the address selector 48, and the count output of the counter 47 is supplied to the address selector 48 via the address conversion circuit 49. Here, the address conversion circuit 49 is a circuit that converts the count data into a read address by referring to a conversion table formed of a ROM. In this case, conversion based on an interleave equation described later is performed. Then, the address selector 48 compares the data supplied from the counter 47 with the address conversion circuit 49.
Is supplied to the memory 42 selectively, and the write address and the read address of the memory 42 are controlled by the data.

In this circuit, for example, the following interleave equation is assumed.

[0010]

I (B, j) = C (n, k)

## EQU2 ## k = 0,1, ‥‥ 455

## EQU3 ## n = 0, {N, N + 1,}

B = B ₀ + 4 · n + k mod (8)

## EQU5 ## j = 2 [(49 k) mod 57] + [(k mod 8) div 4]

By setting the interleave equation, one block data composed of 456 bits is converted into 57 blocks.
The data is divided into eight bits, and the block data 8k, 8
The k + 1,8k + 2,8k + 3rd data is the first half of 4
8k + 4,8k + 5,8k + 6,8k + 7 of the block data interleaved with the even-numbered burst data
The third data is interleaved to the odd number of the latter four burst data, and the combination of block data changes every four bursts at a depth of eight.

The control state of the write address and the read address based on the interleave equation will be described with reference to FIG. 17. A and B in FIG.
Indicates the write state and read state of the block data of
The write address and read address of each of the memories a and b are controlled by an address signal (C in FIG. 17) supplied from the address selector 48. Here, this address signal is supplied to the counter a (46) as shown in FIG.
Becomes the write address, and the output of the address conversion circuit 49 becomes the read address. These count outputs and address conversion outputs are obtained alternately in synchronization with the start signals a and b obtained at the terminals 44 and 45, as shown by E and F in FIG.

As shown in FIG. 17, each of the memories a and b
Since the next block data cannot be written until reading of all block data is completed,
Requires a capacity of at least two blocks.

Although not shown here, the de-interleave circuit for restoring the interleaved data is basically a circuit that performs the reverse processing of the interleave circuit, and therefore requires a memory having the same capacity as the interleave circuit. And

[0015]

As described above, the interleave processing and the de-interleave processing have a disadvantage that a relatively large-capacity memory is required. Here, as the interleaving depth increases, the required memory capacity also increases. Therefore, when performing complicated interleaving, a large-capacity memory is required.

Also, the control circuit of the memory for performing the interleave processing and the de-interleave processing needs to perform complicated control as the complicated interleave is performed, and there is a disadvantage that the circuit scale becomes large.

An object of the present invention is to make it possible to perform complicated interleaving and de-interleaving with a small-capacity memory in this type of transmission apparatus.

Another object of the present invention is to make it possible to control interleave processing and deinterleave processing with a circuit having a simple configuration in this type of transmission apparatus.

[0019]

According to the interleave circuit of the present invention, for example, as shown in FIG. 1, input digital data which has been divided into blocks is temporarily stored in memories 111, 112, and 113, and the memories 111, 112, and 113 are temporarily stored. , 113 in the interleave circuit which interleaves over a plurality of blocks to generate burst data by changing the read order from the memories 111, 11
2,113 are at least a first group of memories 111 and a second
The first group of memories 111 and 113 performs an interleaving process in which the time from when the input digital data is written to the memory to when the digital data is read is relatively short. As the memories 112 and 113,
Interleave processing is performed in which the time from writing of input digital data to memory to reading thereof is relatively long.

Further, the de-interleave circuit of the present invention comprises:
The input digital data interleaved across a plurality of blocks and made into burst data is temporarily stored in a memory, and the order of reading from the memory is changed to the order of writing, thereby restoring block data in the original order. In a de-interleave circuit, a memory is divided into at least a first group and a second group, and the time from when input digital data is written to the memory to when it is read is relatively short as the first group of memories. A deinterleave process is performed, and as a second group of memories, a relatively long time is required from writing input digital data to the memory to reading it out.
The interleaving process is performed.

In the interleave circuit of the present invention, as shown in FIG. 3, for example, input digital data subjected to convolutional encoding is temporarily stored in memories 211 and 212, and the order of reading from the memories 211 and 212 is changed. In an interleave circuit that interleaves over a plurality of blocks to make burst data by changing the write order, the memories 211 and 212 are divided into a plurality of groups al according to a convolutional coding rate, and the memories of each group are divided. Are used in parallel so that the memory of each group is output in parallel.

In this case, the write address and the read address of each group of memories are controlled so as to be the same address, so that the addresses of the memories of each group can be commonly controlled.

Further, the de-interleave circuit of the present invention
The input digital data, which is interleaved over a plurality of blocks to be burst data and is convolutionally coded, is temporarily stored in a memory, and the order of reading from this memory is changed to the order of writing, thereby obtaining the original data. In a de-interleave circuit for restoring block data in order, the memory is divided into a plurality of groups according to a convolutional coding rate, and the memories of each group are used in parallel. This is supplied to a convolutional decoder.

In this case, the write address and the read address of each group of memories are controlled so as to be the same address, so that the addresses of the memories of each group can be commonly controlled.

In the interleave circuit of the present invention, the input digital data which is divided into blocks is temporarily stored in a memory, and the order of reading from the memory is changed to the order of writing, thereby interleaving over a plurality of blocks. In an interleave circuit for generating burst data, the memory is divided into a plurality of groups according to the interleave depth, and control is performed so that the read addresses of the memories in each group are the same.

In this case, convolutionally encoded data is used as input digital data, and the memory is divided into groups of numbers based on the convolutional encoding rate.

Further, in this case, the address of at least one group of memories among the divided groups of memories is
By offsetting a predetermined value, the same address is generated in each group.

Further, the de-interleave circuit of the present invention
For example, as shown in FIG. 9, input digital data interleaved across a plurality of blocks and made into burst data is temporarily stored in memories 311 to 318, and a read order from the memories 311 to 318 is changed to a write order. In the de-interleave circuit for restoring the original order block data, the memories 311 to 318 are divided into a plurality of groups according to the interleave depth,
The read addresses of the memories of each group are controlled so as to be the same address.

In this case, as input digital data, convolutionally encoded data is used, and the memory is divided into groups of numbers based on the convolutional coding rate.

Further, in this case, the addresses of at least one group of memories among the divided groups of memories are
By offsetting a predetermined value, the same address is generated in each group.

[0031]

According to the interleave circuit of the present invention, the memories to be interleaved are divided into a plurality of groups, and the groups used according to the time from writing to reading until reading are written into the memory. A group of memories to which data having a relatively short time from read-in to read-out is written can be written and read in a short cycle, and the capacity of this group of memories can be reduced accordingly.

Further, according to the de-interleave circuit of the present invention, the memory to be de-interleaved is divided into a plurality of groups, and the group used according to the time from writing to reading until reading is divided. In a group of memories to which data with a relatively short time from writing to reading is written, it is possible to perform writing and reading in a short cycle, thereby reducing the capacity of this group of memories. can do.

According to the interleave circuit of the present invention, the memory for the interleave processing is divided into a plurality of groups according to the convolutional coding rate, and the memories of each group are used in parallel. The efficient output of the memory according to the convolutional coding rate is performed by performing the output, and the memory capacity can be reduced and the speed of the memory operation can be reduced accordingly.

In this case, the write address and the read address of each group of memories are controlled so as to be the same, and the address control of each group of memories can be performed in common. The control can be easily performed, and the control circuit for the interleave processing can be simplified.

Further, according to the de-interleave circuit of the present invention, the memory for the de-interleave processing is divided into a plurality of groups according to the convolutional coding rate, and the memories of each group are used in parallel. , The memory is efficiently used in accordance with the convolutional coding rate, so that the capacity of the memory can be reduced and the speed of the memory operation can be reduced.

In this case, the write address and the read address of each group of memories are controlled to be the same address, and the address control of each group of memories can be performed in common. Control is easy, and the control circuit for the de-interleaving process is simplified.

According to the interleave circuit of the present invention, the memory is divided into a plurality of groups in accordance with the interleave depth, and control is performed so that the read addresses of the memories in each group are the same. Can be commonly performed, and the control circuit for the interleave processing can be simplified even when the number of divided memories is large.

In this case, the input digital data is convolutionally encoded data, and the memory is divided into a number of groups based on the convolutional coding rate. Data can be interleaved with simple control.

Further, in this case, the address of at least one group of memories among the divided groups of memories is
Since the same address is generated in each group by offsetting the predetermined value, the address data can be generated only by the offset processing, and the address data can be easily generated.

According to the de-interleaving circuit of the present invention, the memory is divided into a plurality of groups according to the depth of the de-interleaving, and control is performed such that the read addresses of the memories in each group are the same. Thus, the address control of the memories in each group can be commonly performed, and the control circuit for the de-interleave processing can be simplified even when the number of divided memories is large.

In this case, the input digital data is convolutionally coded data, and the memory is divided into groups of numbers based on the convolutional coding rate. Data can be deinterleaved with simple control.

Further, in this case, the address of at least one group of memories among the divided groups of memories is
Since the same address is generated in each group by offsetting the predetermined value, the address data can be generated only by the offset processing, and the address data can be easily generated.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In this embodiment, the interleave circuit in the channel encoder 20 of the transmission system of the portable telephone for performing the digital communication shown in FIGS. 14 and 15 is configured as shown in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, reference numeral 101 denotes a convolutional encoder 22.
FIG. 15 shows terminals to which convolutionally encoded block data output from the terminal 101 is supplied. Block data obtained at this terminal 101 is stored in the memories 111, 112, and 113.
To supply. These three memories 111, 112, 113
Are composed of RAMs, each of which has a capacity to store data for 0.5 block, and which are written in the respective memories and read out from the memories by the address data supplied from the address selector 107 described later. Address is controlled, and a process of interleaving data is performed by controlling the write address. In this case, in this example, data having a relatively short time from writing to reading to the memory is written to the memory 111, and the time from writing to reading to the memory is relatively long. Data is written to the memories 112 and 113. Specific control for selecting the memory to be written will be described later. Note that the block data obtained at the terminal 101 has been subjected to convolutional coding, and is therefore actually two systems of data.

The memories 111, 112, 113
Is supplied to a data selector 102, and the data selected by the data selector 102 under the control of a write / read control circuit 108 described later is output as burst data from an output terminal 103 to a subsequent circuit (FIG. 15). , And performs transmission processing in the transmission circuit to transmit the signal to the base station side.

The memories 111, 112, 11
In order to control the interleave processing in Step 3, the control circuit 30 outputs two types of start signals a and b in synchronization with the output of the block data, and supplies one of the start signals a to the write address generation counter 104. Then, the other start signal b is supplied to the read address generation counter 105.
Then, the address data counted by the counter 104 based on the start signal a is supplied to the address conversion circuit 106, and the write address is converted into an interleaved address according to an interleave equation. This address conversion circuit 106 is constituted by, for example, a ROM table.

Then, the read address data generated by the counter 105 and the write address data converted by the address conversion circuit 106 are transferred to the address selector 10.
7 and the address data selected based on the control of the write / read control circuit 108.
07 to the memories 111, 112, and 113.
Switching between writing and reading in each of the memories 111, 112, and 113 is also performed under the control of the writing / reading control circuit 108. Further, the selection of burst data by the data selector 102 is also performed by the write / read control circuit 10.
8 is performed. In this case, each control by the write / read control circuit 108 is performed based on a control command supplied from the control circuit 30.

Next, the operation of the interleave circuit of this embodiment will be described. First, the interleave equation set here is shown in the following equation.

[0050]

I (B, j) = C (n, k)

## EQU7 ## k = 0,1, ‥‥ 455

## EQU8 ## n = 0, {N, N + 1,}

B = B ₀ + 4 · n + k mod (8)

## EQU10 ## j = 2 [(49 k) mod 57] + [(k mod 8) div 4]

The equations [6] to [10] are the same interleaving equations as the equations [1] to [5] described in the conventional example. Describing each equation, Equation 6 indicates that the k-th data of the n-th block data becomes the j-th data of the B-th burst. Also,
Equation 7 shows that one block data is composed of 456 data from the 0th to the 455th. Equation (8) indicates the number of block data. [Equation 9]
The equation is that the interleave depth is 8, and the first four bursts are 8k, 8k + 1, 8k + 2 of the n-th block data.
It is composed of 8k + 3rd data and 8k + 4,8k + 5,8k + 6,8k + 7th data of the (n-1) th block data, and the latter 4 bursts are composed of 8k + 4,8k + 5,8k + 6,8k + 7th data of the nth block data. , 8k, 8k + of the (n + 1) th block data
The data is composed of 1,8k + 2,8k + 3rd data. The expression (10) indicates a position arranged in a burst.

The operation timing based on the setting of the interleave equation will be described with reference to FIG. 2. Of the block data obtained at the terminal 101 from the convolutional encoder side, 8k, 8k + 1 arranged in the first four bursts , 8
The k + 2, 8k + 3rd data is written into the memory 111 as shown in FIG. 2A, and the 8k + 4, 8k + 5, 8k + 6, 8k + 7th data arranged in the latter four bursts are stored in B and C in FIG. As shown, the data is alternately written into the memory 112 and the memory 113 for each block. Then, when the address signal output from the address selector 107 changes to a write address and a read address in a time sharing manner as shown in FIG. 2D, the written data is sequentially read. The timing shown in FIG.
It indicates whether the address selector 107 selects writing or reading. In this case, the output of the counter 105 is used as the read address as shown in F of FIG. 2, and the output of the address conversion circuit 106 is used as the write address as shown in G of FIG.

As shown in FIG. 2, the 8k + 4,8k + 5,8k + 6,8k + 7th data arranged in the latter four bursts which need to be read from the memory one block later are stored in the two memories 112,113. Since they are stored alternately, the interleaving process is correctly performed according to the above-described interleaving equation. That is, the timing shown in FIG. 2 will be described. For example, when the n-th block data is input, 8k, 8k + 1, 8
The (k + 2, 8k + 3) th data is written into the memory 11
2, 8k + 4, 8k + 5, 8k + 6, 8k + 7th data are written. Then, in the next step, the memory 11
The n-th block data (8k, 8k +
1,8k + 2,8k + 3rd data) and the memory 11
One block before (n-1st block) stored in 3
8k + 4,8k + 5,8k + 6.8 of the block data of
The (k + 7) th data is read out, 8 burst data is created from the data read from both memories, and output from the data selector 102.

Then, when the next (n + 1) th block data is supplied, 8k, 8k +
The 1,8k + 2,8k + 3rd data is written into the memory 111, and the 8k + 4,8k + 5,8k + 6,8k + 7th data is written into the memory 113. Then, in the next step, the (n + 1) th block data (8k, 8k + 1, 8k + 2, 8k + 3rd data) stored in the memory 111 and the block data of the previous block (nth block) stored in the memory 112 8k + 4,8
The (k + 5, 8k + 6, 8k + 7th) data is read, and 8 burst data is created from the data read from both memories and output from the data selector 102.

Hereinafter, similarly, 8k, 8k + 1, 8k + 2, 8k + arranged in the first four bursts of each block.
Writing and reading of the third data to and from the memory 111 are performed for each block, and 8k + 4,8k + 5,8k + 6,8 arranged in the latter four bursts of each block.
Writing and reading of the (k + 7) th data are alternately performed using the two memories 112 and 113.

Since the memories 111, 112, and 113 have a storage capacity of 0.5 block by performing the interleave processing in this manner, the interleave processing is performed with a memory having a total capacity of 1.5 blocks. In this case, the memory capacity is reduced by 0.5 blocks as compared with the conventional example (the example in FIG. 16) that requires two blocks of memory to collectively store the data of each block in the memory (the example of FIG. 16). That is, the memory capacity can be reduced by 25%).

The amount that can be reduced varies depending on the interleave processing state. For example, in the case of the following interleave equation, the memory capacity can be further reduced.

[0058]

## EQU11 ## i (B, j) = C (n, k)

## EQU12 ## k = 0,1, ｋ455

## EQU13 ## n = 0, {N, N + 1,}

B = B ₀ + 4 · n + mod (19) + k div 114

## EQU15 ## j = 2 [(49 k) mod 57] + [(k mod 8) div 4]

When Equations (11) to (15) are set as interleave equations, 18 data × (6 + 1) and 42 data × (5+
1) By adopting a block configuration of 96 data × (5 + 4 + 3 + 2), the storage capacity can be reduced by about 40% as compared with the related art.

In the above-described embodiment, the write address is converted by the address conversion circuit 106 to perform the interleaving process. However, the read address may be converted to the address and subjected to the interleaving process. Further, the memory for performing the interleave processing is constituted by the RAM, but may be constituted by a register. Further, although the address conversion circuit 106 is configured from the ROM table, the address conversion may be performed by arithmetic processing. Further, the counter 104 for generating the write address and the counter 105 for generating the read address may be shared.

Although the above embodiment has been described as an interleaving circuit, the same processing is performed in the case of performing the de-interleaving processing for returning the interleaved data to the original state, so that the de-interleaving processing is performed. The storage capacity of the memory to be performed can be reduced. In this case, the interleaved burst data may be supplied to each of the memories 111, 112, and 113 so that the de-interleaved block data is obtained at the output side of the memory. Circuit 106
The process of converting the address to be converted from the interleaved address to the address of the original block data may be performed.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

In this example, the interleave circuit in the channel encoder 20 of the transmission system of the portable telephone for performing the digital communication shown in FIGS. 14 and 15 is configured as shown in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 3, reference numerals 201 and 202 denote terminals to which two systems of convolutionally encoded block data output from the convolutional encoder 22 (see FIG. 15) are supplied. The supplied block data is supplied to the memories 211 and 212. These two memories 21
1 and 212, the memory 211 has a capacity to store 0.5 blocks of data, and the memory 212 has a capacity to store one block of data. And the memory 21
1 is a storage area divided into four, each of which is a memory a,
b, c, d. The memory 212 is divided into eight storage areas, each of which is a memory e, f, g, h,
i, j, k, l. The number of divisions of the memory is determined by a convolutional coding rate described later (here, a convolutional coding rate 1/2). The divided memories a to a
l has half the storage capacity of one burst of data. In this case, in this example, data having a relatively short time from writing to reading to the memory is written to the memory 211, and a time from writing to reading to the memory is relatively long. Data is written to the memory 212. Specific control for selecting the memory to be written will be described later.

Then, an address selector 208 described later is used.
The address written to each memory and the address read from the memory are controlled by the address data supplied from the side, and the process of interleaving the data is performed by controlling the read address. The data read from each of the memories 211 and 212 is supplied to a data selector 203, and the data selected by the data selector 203 based on the control of a write / read control circuit 209 described later is output as a burst data as an output terminal 204.
To the subsequent stage (the encryption circuit 24 in FIG. 15)
, And the transmission circuit performs a transmission process to transmit the signal to the base station.

Then, in order to control the interleave processing in the circuit of the present embodiment, two types of start signals a and b are output from the control circuit 30 in synchronization with the output of the block data. It is supplied to a read address generation counter 205 and the other start signal b is supplied to a write address generation counter 206. And the counter 20
In step 5, the address data counted based on the start signal a is supplied to the address conversion circuit 207, and the read address is converted into an interleaved address according to an interleave equation. This address conversion circuit 207 is constituted by, for example, a ROM table.

Then, the write address data generated by the counter 206 and the read address data converted by the address conversion circuit 207 are transferred to the address selector 20.
8 and the address data selected based on the control of the write / read control circuit 209.
08 to each of the memories 211 and 212. Switching between writing and reading in each of the memories 211 and 212 is also performed under the control of the writing / reading control circuit 209. Further, the selection of burst data by the data selector 203 is also performed under the control of the write / read control circuit 209. In this case, each control by the write / read control circuit 209 is performed based on a control command supplied from the control circuit 30.

Here, the data processed by the configuration of this example will be described. As shown in FIG. 5, the source data sequence {D ₍₀₎ , D ₍₁₎ , {D _(n) } to be transmitted is , Two encoded data for each source data are generated by the convolutional encoder 22, and 2 ( n + 1) encoded data strings {G0 ₍₀₎ , G0 ₍₁₎ , {G0 _(n) } , ｛G1 ₍₀₎ ,
G1 ₍₁₎ and {G1 _(n) } are supplied to the interleave circuit 23. In this case, the coding rate in the convolutional encoder 22 is １ ／. Then, by the interleave processing in the interleave circuit 23, (k + 1) burst data strings [｛C0 ₍₀₎ , composed of (m + 1) data
C0 ₍₁₎ , {C0 _(m) }, {Ck ₍₀₎ , C
k ₍₁₎ , {Ck _(m) }] is generated.

FIG. 6 shows a configuration example of the convolutional encoder in this case.
In this case, the source data string {D_(0),
D_(1),‥‥ D_(n)｝ Is a D flip-flop connected in four stages
Rops 242, 243, 244 and 245,
The data obtained at the terminal 241 and the D flip-flop 2
44 and the output of the D flip-flop 245,
The exclusive OR is supplied to the Ex-OR gate 246,
G0 series block data string {G0_(0),G0_(1),‥‥ G
0_(n)｝ Is obtained at the terminal 247. Also, the terminal 241
Data, the output of D flip-flop 242, and D
Output of flip-flop 244 and D flip-flop
245 is supplied to an Ex-OR gate 248 to be discharged.
The logical OR is calculated and the G1 series block data string {G1
_(0),G1 _(1),‥‥ G1_(n)Is obtained at the terminal 249.

Next, the operation of the interleave circuit of this embodiment will be described. The interleave equation set here is
[Equation 6] to [Equation 1] described in the first embodiment.
[0], the operation timing of each of the memories a to l is shown in FIG. 4A to 4L show the data write and read states of the memories a to l.
Among the block data obtained in 1,202, {G0
_{(4n) The} ｝ th data is written to the memory a, and the ｛G
1 _(4n) ｝ th data is written to memory b, and {G0
_{(4n + 1)} ｝ th data is written to the memory c, and ｛G1
_{(4n + 1)} ｝ th data is written into the memory d, and ｛G0
_{(4n + 2)} ｝ th data is written to memory e or i,
{G1 _{(4 n + 2)} } -th data is written to memory f or j, {G0 _{(4n + 3)} }-th data is written to memory g or k, and {G1 _{(4n + 3)} ｝ Th data is memory h or l
Is written to.

Here, in the memories e to l formed by dividing the memory 212, the memories e, f, g, h and the memories i, j, k, l are used alternately for each block. It will be used in eight burst periods. That is, FIG.
As shown in (1), when one block of data is input at a certain timing, this one block of data is divided into eight and stored in the memories a to h. Then, after the data is stored, the stored data is sequentially read as burst data.
At the time of this reading, the data stored in the memories a to d are read in the order of the memories a, b, c, and d, and the data stored in the memories i to j at the timing one block before are stored in the memories i, j, and i. The data is read out in the order of k and l and is interleaved as four burst data. That is, the data of the first burst is composed of the output of the memory a and the output of the memory i, the data of the next burst is composed of the output of the memory b and the memory j, and the data of the next burst is the data of the memory c. The last burst data is composed of the output of the memory d and the memory l.

The data of one block supplied at the next timing is stored by using the memories a to d and the memories i to l, and after this storage, the data stored in the memories a to d and 1 Memory e at timing before block
.. To h are sequentially read out and similarly made four burst data. This control of the memory is repeated every time eight bursts of data are output.

By performing the interleave processing as described above, the storage capacity of each of the memories 211 and 212 is 1.5 blocks in total, and the interleave processing is performed by the memory having the capacity of 1.5 blocks. In order to store the data of each block collectively in the memory,
As compared with the conventional example requiring the memory for blocks (the example in FIG. 16), the memory capacity for 0.5 blocks is reduced (that is, 25%).
Memory capacity). In this example, the memory 211 storing data having a relatively short time from writing to reading is divided into four memories a to d, and the time from writing to reading is compared. By dividing the memory 212 in which the long data is stored into eight and dividing them into memories e to l, writing the block data in eight of the memories a to l in parallel,
The data write speed and data read speed are reduced to 1/8.
As described above, the data write speed and the read speed are greatly reduced, so that the frequency of the memory drive signal can be reduced.
The power consumption of the interleave circuit can be reduced, the circuit configuration itself is simplified, and the interleave circuit can be made compact. In this case, since the numbers of divisions of the memories 211 and 212 are determined in accordance with the convolutional coding rate, the parallel processing of the convolutionally coded block data is favorably performed.

In the second embodiment, the read address is converted by the address conversion circuit 207 to perform the interleaving process. However, the write address may be converted to the address to perform the interleaving process. The memory for performing the interleave processing is R
Although constituted by AM, it may be a register. Further, although the address conversion circuit 207 is configured from a ROM table, the address conversion may be performed by arithmetic processing. Also, a counter 2 for generating a write address
06 and the read address generation counter 205 may be shared.

Although the second embodiment has been described as an interleave circuit, a similar process is performed when a de-interleave process for restoring interleaved data is performed. Reduction of the storage capacity of the memory that performs the interleave processing, writing of the memory,
The reading speed can be reduced. In this case, the interleaved burst data may be supplied to each of the memories 211 and 212 so that the deinterleaved block data can be obtained at the output side of the memory. The process of converting the address to be converted from the interleaved address to the address of the original block data may be performed.

Here, a data example in the case of performing the deinterleave processing at the time of reception will be described. As shown in FIG. 7, (k + 1) burst data composed of (m + 1) received data Column [｛u0 _(0), u0
_(1), ‥‥ u0 _(m) ｝, ‥‥ ｛Ck _(0), Ck _(1), ‥‥ Ck
_(m) ｝] is de-interleaved by the de-interleave circuit 12 to obtain 2 (n + 1) block data strings {u ′ _(0), u ′ _(1), ‥‥ u ′ _{(2n + 1) )} ｝. Then, the source data sequence {d _(0), d _(1), {d _(n) } is obtained by Viterbi decoding at a coding rate of 1/2 in the Viterbi decoder 13.
Is generated.

FIG. 8 shows an example of a branch metric calculation circuit in Viterbi decoding, which is an interface between de-interleaving processing and Viterbi decoding. Here, the block data sequence {u ′ _(0), u ′ _(1), {u ′ _{(2n + 1)} } output from the de-interleave circuit is sent to the latch circuits 222 and 223 via the terminal 221. Supply.
Each of the latch circuits 222 and 223 performs primary holding at a predetermined timing, and performs a data sequence ｛u ′ _(0), u ′ _(2), ‥‥ u ′ corresponding to an encoding generation polynomial.
_(2n) } and {u ′ _(1), u ′ _(3), {u ′ _{(2n + 1)} }. Then, according to the coding rate, two data {u '
_(0), u ' ₍₁₎ ｝, ｛u' _(2), u ' ₍₃₎ ｝, ‥‥ ｛u'
_(2n) , u ′ _{(2n + 1)} } are used to supply the respective branch metric calculation circuits 231, 232, 233, and 234 to calculate the corresponding branch metrics.

In this case, by applying the de-interleave processing of this embodiment, parallel processing is performed in accordance with the convolutional coding rate. Therefore, each branch metric is not latched by the latch circuits 222 and 223. The calculation of the branch metric can be performed by the calculation circuits 231 to 234, and the configuration of the Viterbi decoder can be simplified accordingly. As described above, according to the present embodiment, the de-interleave processing is performed well.

Next, a third embodiment of the present invention will be described with reference to FIGS.
3 will be described.

In this example, the de-interleave circuit in the channel decoder 20 of the receiving system of the portable telephone for performing the digital communication shown in FIGS. 14 and 15 is configured as shown in FIG. 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 9, reference numeral 301 denotes a terminal to which the burst data output from the decryption circuit 11 (see FIG. 15) is supplied, and the burst data obtained at this terminal 301 is supplied to the memories 311 to 318. The eight memories 311 to 318 have a total storage capacity of two blocks of data. Even-numbered data of burst data obtained at the terminal 301 is stored in the memories 311 to 314, and odd-numbered data is stored in the memories 311 to 314. Stored in the memories 315 to 318. In this example, the write addresses to the memories 311 to 314 in which even-numbered data are stored are sequentially offset by −16, and the write addresses to the memories 315 to 318 in which odd-numbered data are stored are It is sequentially offset by {(−16) + (− 32)}.

Then, the address written to each memory and the address read from the memory are controlled by the address data supplied from the address counter 303, and the data is deinterleaved by controlling the read address. In this case, the address counter 303 is configured by a gate circuit, and the generation of the write address and the read address in the address counter 303 is performed under the control of the control circuit 30. And
The data read from each of the memories 311 to 318 is supplied to a data selector 302, and the two data selected by the data selector 302 under the control of the control circuit 30 are output as convolutionally encoded block data. The signals are supplied from terminals 304 and 305 to a subsequent circuit (Viterbi decoder 13 in FIG. 15) to be decoded.

Then, in order to control the de-interleave processing in the circuit of this embodiment, the control circuit 30 supplies write / read control signals directly to the memories 311 to 318 in synchronization with the supply of burst data. , The control signal is also directly supplied to the data selector 302.

Next, the operation of the interleave circuit of this embodiment will be described. First, the interleave equation set here is shown in the following equation.

[0085]

## EQU16 ## i (B, j) = C (n, k)

## EQU17 ## k = 0,1, ‥‥ 455

## EQU18 ## n = 0, {N, N + 1,}

B = B ₀ + 4 · n + k mod (4)

J = 2 [(49 k) mod 57] + [(k mod 8) div 4]

The equations (16) to (20) will be described. The equation (16) indicates that the k-th data of the n-th block data is the j-th data of the B-th burst. . The expression (17) indicates that one block data is composed of 0-th to 455-th 456 data. Equation (18) indicates the number of block data. Expression (19) shows that the interleave depth is 4, and the 4th, 4k + 1, 4
k + 2, 4k + 3rd data are 4n and 4n respectively
+1, 4n + 2, 4n + 3 indicates that they are arranged in the third burst. The expression (20) indicates the position of data arranged in each burst.

By setting the interleave equation,
When each interleaved burst data is divided into odd-numbered data and even-numbered data, the block data included in each burst is 8k-th and 8k + 4
8th, 8k + 1th and 8k + 5th, 8k + 2nd and 8th
The (k + 6) th, (8k + 3) th, and (8k + 7) th positions are arranged to be offset by −63, respectively, and the 4k, 4k + 1, 4k + 2, 4k + 3rd data are arranged to be offset by −16 between each burst data.

The operation timing of the circuit of this embodiment based on the setting of the interleave equation will be described with reference to FIG. 10. Interleaved burst data # i0 _(0), # i0 ₍₁₁₃₎ obtained at terminal 301 ｝, ｛I1 _(0),
‥‥ i1 ₍₁₁₃₎ ｝, ｛i2 _{(0 ),} ‥‥ i2 ₍₁₁₃₎ ｝, ｛i
3 _(0), {i3 ₍₁₁₃₎ }, even-numbered data {i
0 _(0), i0 _(2), ‥‥ i0 ₍₁₁₂₎ ｝, ｛i1 _(0), i1 _(2),
‥‥ i1 ₍₁₁₂₎ ｝, ｛i2 _(0), i2 _(2), ‥‥ i
2 ₍₁₁₂₎ }, {i3 _(0), i3 ₍₂₎ , {i3 _{( 112)} } are respectively stored in the memories 311, 312, and 313 as shown in FIGS. , 314 sequentially. In this case, each of the memories 311, 312, 313,
The write address to 314 is sequentially offset by -16.

Similarly, odd-numbered data {i0 _(1), i0 ₍₃₎ , {i0 _{(113 )} }, {i1 _(1), i of the burst data
1 _(3), ‥‥ i1 ₍₁₁₃₎ ｝, ｛i2 _(1), i2 _(3), ‥‥ i2
_{(113 )} }, {i3 _(1), i3 ₍₃₎ , {i3 _{( 113)} } are respectively stored in the memories 315, 316, 317, as shown in FIG. 318 are sequentially stored. In this case, the memories 315, 316, 31
7, 318 are sequentially written to $ (-16) +
(−32) Offset by｝.

By setting the write address in this manner, the data numbers 8k, 8k + 1,.
8k + 7 are stored at the same address in the memories 311 to 318, respectively.

The data written in this manner is read out according to the interleave pattern in accordance with each of .DELTA.C
_(0), C _(7), ‥‥ C _(8k) ｝, ｛C _(1), C _(8), ‥‥
The read address is set to the address counter 30 so that the read address is read in the order of C _{(8k + 1)} }, {C _(7), C _(15), {C _{(8k + 7)} }.
3 and performed as shown in FIG. Then, the data selector 302 supplies the even-numbered block data sequence {C _(0), C _(2), {C ₍₁₁₂₎ } of the block data to the output terminal 304 in this order, and the odd number of the block data.番 目 C _(1), C _(3), ‥‥ C
₍₁₁₃₎ are supplied to the output terminal 305 in this order.

The writing and reading processes are repeated every time four burst data are input, to generate a block data string.

By performing the de-interleaving process in this way, the write addresses and read addresses of the eight divided memories 311 to 318 are all the same, and the address control of the memories can be easily performed. Therefore,
The address counter 303 can be constituted by a simple logic gate, and the counter for generating the write address and the counter for generating the read address can be easily shared. Therefore, the circuit scale of the de-interleave circuit can be reduced, and the power consumption can be reduced.

Although the deinterleaving circuit has been described in the above embodiment, the same processing can be performed in the case of performing the interleave processing, so that the control system of the interleave processing can be simplified. In this case, block data may be supplied to each of the memories 311 to 318 so that interleaved burst data is obtained at the output side of the memory.

Here, an example of a circuit configuration facing the address counter 303 is shown in FIG. In the example of FIG. 11, two RAMs 421 and 422 for storing even-numbered bit data and two RAMs 423 and 424 for storing odd-numbered bit data are used as memories for de-interleave processing. From the circuit 30 side, a data start signal S11 is obtained at a terminal 401, and a write / read control signal is obtained at a terminal 402. Further, data S13 of the burst number is obtained at the terminal 403. The 1-bit counter 404 determines whether the data start signal S11 is an odd bit or an even bit, and the determination signal S14 is supplied to the even bit address counter 410a and the odd bit address counter 410b. Further, the burst number data S13 is supplied to a selector 405a for setting an even-numbered bit initial address to generate even-numbered bit initial address data S15, and is also supplied to a selector 405b for setting an odd-numbered bit initial address. , Odd-numbered bit initial address data is generated.

Then, the even-numbered bit address counter 4
10a includes two 3-bit counters 411 and 412 for creating address data, a selector 416 for controlling both counters 411 and 412, and logic gates 413 and 41.
4,415,417, and the data start signal S11
, An even / odd discrimination signal S14, even bit initial address data S15, and a write / read control signal. In this case, the upper three bits of address data S16 are created by the counter 411, and the lower three bits of address data S19 are created by the counter 412.

According to the even-bit address counter 410a of the configuration of the present example, as shown in FIG. 12, the upper 3 bits of address data S16 (FIG. 12F) are replaced with the lower 3 bits of address data S19 (FIG. 12). When I) is other than "0", "0" to "6" are repeated, and when the lower 3-bit address data S19 is "0", the address data sequentially changes from "0" to "7". The lower three bits of the address data S19 are replaced with the upper three bits of the address data S16.
When it returns to “0”, it decreases by one. In order to control the count value, the logic gate 413 detects that the count output of the 3-bit counter 411 is "6" (the detection signal S17 of G in FIG. 12), and the count output of the 3-bit counter 411 is changed. "7" is detected by the logic gate 414 (H detection signal S18 in FIG. 12),
The logic gate 415 detects that the count output of the 3-bit counter 412 is "7" (the detection signal S20 of J in FIG. 12). By selecting the respective logical outputs by the selector 416, the control signals S21
(K in FIG. 12) is created. Also, the logic gate 417
In this case, the lower three bits of the address data S19 are "6".
Thus, when the address data S16 of the upper three bits is "2", a control signal for resetting each of the 3-bit counters 411 and 412 to "0" is generated. Note that the counter data display here is hex display.

Then, the even-numbered bit address counter 4
The address data created in 10a is stored in the RAMs 421, 4
Then, the burst data obtained at the terminal 406 is written to the RAMs 421 and 422 by writing even-numbered bits of data.

The odd bit address counter 41
0b is similarly configured, and the writing of odd-numbered bit data of the burst data obtained at the terminal 406 to the RAMs 423 and 424 is controlled. However, the odd bit initial address data is supplied to the odd bit address counter 410b instead of the even bit initial address data S15.

In reading data from each of the RAMs 421 to 424, address data for sequential reading is created as shown in FIG. That is, when the data start signal S11 (A in FIG. 13) is supplied at the data read timing, the read addresses of the RAMs 421 and 422 (B in FIG. 13, in the case of even-numbered bits) are created,
In each of the address counters 410a and 410b, “0” to
Address data is sequentially created up to "39" (hex display), and the corresponding RAM 421, 422 or 423, 424
To supply.

By supplying this address data, each RA
Stored from M421 to 424 to C to F in FIG.
Data is read, and a selection signal is supplied to data selector 407.
The RAMs 421 and 422 are supplied by the supply of S26 (G in FIG. 13).
The data read from is alternately selected and the even data
S27 (H in FIG. 13) is created, and the RAM 42
3,424 are alternately selected and read
Number data S28 (I in FIG. 13) is created, and both data S
27 and S28 from the terminals 408 and 409 to the Viterbi decoder side
Supplied to The data read from the RAM 421
As the data S22, the block data string $ C_(0),C_(2),C
_(8),C_(Ten),C_(16),‥‥ C₍₄₅₀₎｝, RAM4
Data S23 read from block 22 includes block data.
Data train ｛C_(1),C_(3),C_(9),C_(11),C_(17),‥‥ C
₍₄₅₁₎And the data S read from the RAM 423
24, the block data string $ C_(Four),C_(6),C
_(12),C _(14),C_(20),‥‥ C₍₄₅₄₎｝, RAM
Data S25 read from 424 is a block
Data string $ C_(Five),C_(7),C_(13),C_(15),C_{(twenty one),}‥‥
C ₍₄₅₅₎It becomes｝.

Here, the address counter 303 is constituted by a logic gate as shown in FIG. 11, but the address counter 303 is formed by using a ROM table.
03 can also be configured. In this case, since the addresses of the respective memories are common, the capacity for storing the conversion data of the ROM table can be reduced to 1/8 of the conventional capacity.

The values such as the number of divisions of the memory shown in each of the above embodiments are obtained by selecting the optimum values based on the conditions such as the interleave equation and the convolutional coding rate applied in each embodiment. In some cases, when conditions such as the interleave equation change, it may be possible to perform better processing by changing the number of divisions of the memory.

In each of the above-described embodiments, the interleaving circuit and the de-interleaving circuit of the transmission data when the communication is performed between the base station and the terminal station (portable telephone) have been described. Circuit or
Of course, it can be applied to an interleave circuit.

[0105]

According to the interleave circuit of the present invention,
Dividing the memory to be interleaved into multiple groups,
By dividing the group to be used according to the time from writing to the memory to reading, the memory of the group to which data with a relatively short time from writing to the memory to reading is written is
Writing and reading can be performed in a short cycle, and the capacity of this group of memories can be reduced accordingly.

According to the de-interleaving circuit of the present invention, the memory to be de-interleaved is divided into a plurality of groups, and the groups used according to the time from writing to reading to the memory are divided. In a group of memories to which data with a relatively short time from writing to reading is written, it is possible to perform writing and reading in a short cycle, thereby reducing the capacity of this group of memories. can do.

According to the interleave circuit of the present invention, the memory for the interleave processing is divided into a plurality of groups according to the convolutional coding rate, and the memories of each group are used in parallel. The efficient output of the memory according to the convolutional coding rate is performed by performing the output, and the memory capacity can be reduced and the speed of the memory operation can be reduced accordingly.

In this case, the write address and the read address of each group of memories are controlled so as to be the same, and the address control of each group of memories can be performed in common. The control can be easily performed, and the control circuit for the interleave processing can be simplified.

Further, according to the de-interleave circuit of the present invention, the memory for the de-interleave processing is divided into a plurality of groups according to the convolutional coding rate, and the memories of each group are used in parallel. , The memory is efficiently used in accordance with the convolutional coding rate, so that the capacity of the memory can be reduced and the speed of the memory operation can be reduced.

In this case, the write address and the read address of each group of memories are controlled so as to be the same address, and the address control of each group of memories can be performed in common. Control is easy, and the control circuit for the de-interleaving process is simplified.

According to the interleave circuit of the present invention, the memory is divided into a plurality of groups according to the interleave depth, and the read addresses of the memories in each group are controlled so as to be the same. Can be commonly performed, and the control circuit for the interleave processing can be simplified even when the number of divided memories is large.

Also, in this case, the input digital data is convolutionally encoded data, and the memory is divided into a number of groups based on the convolutional coding rate. Data can be interleaved with simple control.

Further, in this case, the address of at least one group of memories among the divided groups of memories is
Since the same address is generated in each group by offsetting the predetermined value, the address data can be generated only by the offset processing, and the address data can be easily generated.

According to the de-interleaving circuit of the present invention, the memory is divided into a plurality of groups in accordance with the depth of the de-interleaving, and control is performed such that the read addresses of the memories in each group are the same. Thus, the address control of the memories in each group can be commonly performed, and the control circuit for the de-interleave processing can be simplified even when the number of divided memories is large.

In this case, convolutionally encoded data is used as input digital data, and the memory is divided into groups of numbers based on the convolutional coding rate. Data can be deinterleaved with simple control.

Further, in this case, the address of at least one group of memories among the divided groups of memories is
Since the same address is generated in each group by offsetting the predetermined value, the address data can be generated only by the offset processing, and the address data can be easily generated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart according to the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart according to a second embodiment.

FIG. 5 is an explanatory diagram showing a convolutional encoding state and an interleave state according to the second embodiment.

FIG. 6 is a configuration diagram illustrating a convolutional encoder according to a second embodiment.

FIG. 7 is an explanatory diagram showing a Viterbi decoding state and a deinterleaving state of the second embodiment.

FIG. 8 is a configuration diagram illustrating a branch metric calculation circuit at the time of Viterbi decoding according to the second embodiment.

FIG. 9 is a configuration diagram showing a third embodiment of the present invention.

FIG. 10 is a timing chart according to a third embodiment.

FIG. 11 is a circuit diagram of a deinterleave circuit according to a third embodiment.

FIG. 12 is a timing chart showing a write state of the de-interleave circuit shown in FIG. 11;

FIG. 13 is a timing chart showing a read state of the de-interleave circuit shown in FIG. 11;

FIG. 14 is a configuration diagram illustrating an example of a mobile phone.

15 is a configuration diagram of a channel encoder and a channel decoder of the example of FIG.

FIG. 16 is a configuration diagram showing an example of a conventional interleave circuit.

FIG. 17 is a timing chart showing an interleaved state in the example of FIG. 16;

[Explanation of symbols]

Reference Signs List 30 control circuit 102 data selector 104 write address generation counter 105 read address generation counter 106 address conversion circuit 107 address selector 108 write / read control circuit 111, 112, 113 memory 203 data selector 205 read address generation counter 206 write address generation Counter 207 address conversion circuit 208 address selector 209 write / read control circuit 211, 212 memory 302 data selector 303 address generation counter 311, 312, 313, 314, 315, 316, 3
17,318 memory

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 13/00

Claims (12)

(57) [Claims] An interleaving method for interleaving over a plurality of blocks to form burst data by temporarily storing input digital data in blocks in a memory and changing a reading order from the memory to a writing order. In the circuit, the memory is divided into at least a first group and a second group, and as a memory of the first group, a time from writing of the input digital data to the memory to reading thereof is relatively short. An interleave circuit that performs short interleave processing and performs interleave processing as a memory of the second group that takes a relatively long time from writing of the input digital data to the memory to reading thereof. 2. Input digital data interleaved over a plurality of blocks to form burst data,
A de-interleave circuit that temporarily stores the data in a memory and changes the order of reading from the memory to the order of writing to restore block data in the original order, wherein the memory includes at least a first group and a second group. The first group of memories performs a de-interleaving process in which the time from when the input digital data is written to the memory to when the input digital data is read out is relatively short. As the second group of memories, A de-interleave circuit for performing a de-interleave process in which the time from writing of the input digital data to the memory to reading thereof is relatively long. 3. The convolutionally coded input digital data is temporarily stored in a memory, and a read order from the memory is changed to a write order, thereby interleaving over a plurality of blocks to generate burst data. An interleave circuit which divides the memory into a plurality of groups according to the convolutional coding rate, uses the memories of each group in parallel, and outputs the data in parallel from the memories of each group. . 4. A write address and a read address of the memories of each group are controlled to be the same address,
4. The interleave circuit according to claim 3, wherein the address control of the memories of each group can be commonly performed. 5. An input digital data which is interleaved over a plurality of blocks to be burst data and is convolutionally coded is temporarily stored in a memory, and a reading order from the memory is changed to a writing order. In the de-interleaving circuit for restoring the original order block data, the memory is divided into a plurality of groups according to the convolutional coding rate, and the memories of each group are used in parallel. A de-interleave circuit that supplies the output of the memory to the convolutional decoder in parallel. 6. The write address and the read address of the memories of each group are controlled to be the same address,
6. The de-interleave circuit according to claim 5, wherein address control of each group of memories can be commonly performed. 7. Interleaving is performed by temporarily storing input digital data in blocks in a memory and changing the order of reading from the memory to the order of writing to interleave over a plurality of blocks to form burst data. An interleave circuit for dividing the memory into a plurality of groups according to a depth of the interleave, and controlling the read addresses of the memories in each group to be the same. 8. The interleave circuit according to claim 7, wherein convolutionally encoded data is used as the input digital data, and the memory is divided into groups of numbers based on the convolutional coding rate. 9. The same address is generated in each group by offsetting a predetermined value with respect to an address of at least one group of memories among the divided groups of memories. Interleave circuit. 10. Input digital data interleaved as a burst data over a plurality of blocks is temporarily stored in a memory, and the order of reading from the memory is changed to the order of writing, whereby the original order of the data is restored. A de-interleave circuit for restoring block data, wherein the memory is divided into a plurality of groups in accordance with the interleave depth, and the read addresses of the memories in each group are controlled to be the same address. . 11. The de-interleave circuit according to claim 10, wherein the input digital data is convolutionally encoded data, and the memory is divided into groups of numbers based on the convolutional coding rate. . 12. An apparatus according to claim 10, wherein the same address is generated in each group by offsetting a predetermined value with respect to an address of at least one group of the divided memories. De-interleave circuit.