KR100239727B1 - Encoder of cellullar system - Google Patents

Abstract

The present invention relates to an encoding apparatus of a cellular system, and more particularly, to store frame data in a memory, access the data in an interleaved output order, and generate five symbols for each 10-bit access data. It is designed to reduce the size of the memory and the efficient use of the memory by configuring to select the number of symbols. The present invention provides a frame data generation unit 201 for outputting frame data as input of data RAW-DATA, a deflip-flop 205 for latching output data of the frame data generation unit 201, and A memory block 203 for storing the output data from the deflip-flop 205, outputting the data in the order to be interleaved, and storing the interleaved symbol data, and encoding data output from the memory block 203 to 5 per 10 bits. Generating a plurality of symbols, selecting three of them, and outputting them to the memory block 203, and a de-flip which latches and transmits the interleaved symbol data output from the memory block 203 to the outside And a microprocessor 204 for controlling the operation of the flop 206, the frame data generator 201, the encoder 202, and the memory block 203.

Description

ENCODER OF CELLULLAR SYSTEM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to cellular systems, and more particularly, to an apparatus for encoding a cellular system adapted to be suitable for a cellular system employing a CDMA scheme.

In the prior art, as shown in the block diagram of FIG. 1, a frame data generation unit 101 for outputting frame data by inputting data (RAW-DATA) and frame data of the frame data generation unit 101 are input. An encoder 102 for generating symbol data, a memory block 103 for interleaving by storing the symbol data, and outputting the data in units of rows, and the frame data generator 101, an encoder 102, and a memory block. It consists of a microprocessor 104 that controls the operation of 103.

The memory block 103 includes a RAM 111 for storing encoded symbol data, an address decoder 112 for decoding an address under the control of the microprocessor 104, and applying the same to the RAM 111. And an input / output buffer 113 for inputting the output data of the 102 to the RAM 111 and transmitting the output data of the RAM 111 to the outside.

Referring to the operation of the prior art as follows.

The frame data generation unit (CRC & Tail BIT) 101 receives the data (RAW-DATA) and completes the complete frame data.

In this case, if the order of the input data is changed, the value of the CRC is also changed, so that the order of the input data cannot be arbitrarily changed.

If the data rate is full rate in the CDMA scheme, data of one frame is 'D1 to D192' and the data D1 to D192 is input to the encoder 102.

The convolutional encoder 102 consists of an 8-bit shift register to make three symbols per data input.

If the data rate is full, the encoder 102 outputs the symbol data C1 to C576 to the memory block 103 with respect to the input data D1 to D192 of one frame.

In this case, the memory block 103 has an input / output buffer 113 connected to the output terminal of the encoder (102) to the input terminal of the RAM (111) so that the output data of the encoder (102) in the column unit (RAM) 111).

Thereafter, when the symbol data of one frame unit is all stored in the RAM 111, the input / output buffer 113 connects the output terminal of the RAM 111 to the outside.

Accordingly, the symbol data stored in the RAM 111 is output to the outside in units of rows.

That is, the RAM 111 stores and outputs symbol data as shown in FIG. 2, and after one symbol frame is completely input to the memory, the encoded symbol frames are 'C1 C33C65 ... C545, C2C34C66. Interleaving is performed by outputting in order of .. C546, ..., C32C64C96 ... C576 '.

In this case, since the row order of the data output from the RAM 111 changes according to the data rate of the frame, other symbol frames cannot share the same memory space.

In the above, an area for data input / output of the RAM 111 is designated by a corresponding address decoded by the controlled address decoder 112 of the microprocessor 104.

In the CDMA cellular system for sequential symbol transmission, since the interleaved symbols always define a constant symbol rate, the above operation is continuously performed. The encoded symbols are stored in a memory corresponding to one symbol frame size. In this case, interleaving is performed when symbol data of one frame is stored, and coded symbols generated during the symbol interleaving process are repeatedly interleaved at a constant speed while repeatedly storing data in another memory region. Outputs symbol data.

Therefore, in order to have a constant symbol rate at all times, a memory having a data access rate that is twice the size of '1 / (encoding rate) * frame bit * 2' and the data rate is required.

However, this conventional technique requires two frame symbol size memory to always maintain a constant output symbol rate regardless of the input data rate during encoding / decoding. Therefore, when one logic is implemented, the overall size of the ASIC chip is increased. Of course, manufacturing costs are rising.

In order to solve the problems of the prior art, the present invention stores frame data in a memory and accesses them in an output order of interleaved data, and generates five symbols per 10 bits for each accessed data to select three symbols among them. It is an object of the present invention to provide an encoding apparatus of a cellular system invented so that the memory can be efficiently used and the size of the memory can be reduced.

1 is a block diagram of a coding apparatus of the prior art.

FIG. 2 is an exemplary view illustrating a storage state of a RAM in FIG. 1.

3 is a block diagram of an embodiment according to the present invention.

4 is an exemplary view illustrating a storage state of a RAM in FIG. 3.

5 is a detailed block diagram of the encoder in FIG.

6 is an operation timing diagram in FIG. 3.

7 is a table showing data fetch and symbol selection in FIG.

*** Description of the symbols for the main parts of the drawings ***

201: frame data generator 202: encoder

203: Memory block 204: Microprocessor

205,206: flip-flop 211: RAM

212: address decoder 213: input / output buffer

221, 224 latch unit 222 logical operation unit

223 multiplexer 225 2-bit counter

226: symbol selector 227, 229: end gate

228: Inverter

The present invention provides a first latch means for latching frame data, a memory block for storing output data from the latch means, outputting the data in an order to be interleaved, and storing interleaved symbol data; Encoding means for generating a predetermined symbol per predetermined bit of data output from the block and selecting any number of symbols to the memory block; and latching interleaved symbol data output from the memory block to the outside. And second latch means for transmitting, and means for controlling the respective means.

The memory block includes a RAM for storing output data from the first latching means and outputting the data in an order to be interleaved, and an address decoder for designating a corresponding region of the RAM by decoding an address under control of a control means. And by applying the output data of the first latching means to the RAM and the output data of the RAM to the encoding means under the control of the control means. RAM) and an input / output buffer for transmitting interleaved symbol data output from the RAM to a second latching means.

The encoding means comprises: a first latch unit for latching 10-bit output data of the memory block, a logic operation unit for exclusively ORing the output data of the latch unit two by two, and outputting five symbol data, and three of the output data of the logic operation unit; A 5 * 3 multiplexer for selecting two pieces, a second latch portion for latching the output data of the 5 * 3 multiplexer and outputting the output data to the memory block, and an output signal of a 2-bit counter to be input to the multiplexer. A symbol selector for outputting a switching signal, a first AND gate for controlling the operation of the first latch unit by ANDing the second and third clocks, an output signal of the inverter for inverting the third clock, and the second clock. And a second AND gate for controlling the operation of the second latch portion by logical multiplication.

Hereinafter, the present invention will be described in detail with reference to the drawings.

3 is a block diagram showing an embodiment of the present invention. As shown therein, a frame data generation unit 201 for outputting frame data by inputting data RAW-DATA and the frame data generation unit 201 are shown. A deflip-flop 205 for latching the output data of the memory, a memory block 203 for storing the output data from the de-flip-flop 205, outputting the data in an order to be interleaved, and storing the interleaved symbol data; The encoder 202 encodes the data output from the block 203 to generate five symbols per 10 bits, selects three symbols from the block 203, and outputs the selected symbols to the memory block 203, and from the memory block 203. A de-flip flop 206 for latching the output interleaved symbol data to be transmitted to the outside, and a microprocessor 204 for controlling operations of the frame data generator 201, the encoder 202, and the memory block 203. It consists of.

The memory block 203 stores the output data from the flip-flop 205 and outputs the RAM 211 in the order to be interleaved, and decodes the address under the control of the microprocessor 204. An address decoder 212 that designates a corresponding region of the memory and the output data of the flip-flop 205 to the RAM 211 under the control of the microprocessor 204 and output data of the RAM 211. Is applied to the encoder 202 to store the output symbols of the encoder 202 in the RAM 211 and to transmit the interleaved symbol data in the RAM 211 to the flip-flop 206. ).

As shown in the block diagram of FIG. 5, the encoder 202 includes a first latch unit 221 for latching the 10-bit output data of the memory block 203, and output data of the latch unit 221. A logical arithmetic unit 222 for outputting five symbol data by exclusive OR of each one, a 5 * 3 multiplexer 223 for selecting three of the output data of the logical arithmetic unit 222, and the 5 * 3 multiplexer 223 A switching signal (S1) (S2) to the multiplexer (223) with the second latch unit (224) for latching the output data of the output block to the memory block (203) and the output signal of the 2-bit counter (225). A symbol selector 226 for outputting the signal, an AND gate 227 for controlling the first latch unit 221 by ANDing the clocks CLK2 and CLK3, and an inverter 228 for inverting the clock CLK3. An AND signal 229 for controlling the second latch unit 224 by performing an AND operation on the output signal and the clock CLK2 is performed.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

The frame data generator 201 generates complete frame data by adding the CRC and Tail bits as input to the data RAW-DATA, and the deflip-flop 205 latches the output data of the frame data generator 201. To be output to the memory block 203.

At this time, the memory block 203 is controlled by the microprocessor 204, and the input / output buffer 213 forms a data transfer path from the deflip-flop 205 to the RAM 211, and thus from the de-flip-flop 205. The output data is stored in the corresponding area of the RAM 211.

Thereafter, when one frame of data is stored in the RAM 211, the input / output buffer 213 forms a data transmission path from the RAM 211 to the encoder 202 under the control of the microprocessor 204.

Accordingly, when frame data is output in the order to be interleaved from the memory block 203, the encoder 202 generates five symbols per 10-bit data, and selects only three symbols among the generated five symbols to select the memory block ( 203 is output to the corresponding area of the RAM 211.

Thereafter, the memory block 203 stores the three symbol data in the RAM 211 because the input / output buffer 213 forms a data transmission path from the RAM 211 to the outside under the control of the microprocessor 204. do.

Thereafter, while forming the symbol data in the encoder 202, the symbol data immediately stored in the RAM 211 is output to the outside.

This operation is repeated continuously, whereby interleaved symbol data is output to the outside at a constant speed.

In the above operation, the frame data and the encoded symbol data are stored in the RAM 211 as illustrated in FIG. 4.

The operation of the encoder 202 will be described in detail as follows.

When one frame of data is stored in the RAM 211, the data stored in the RAM 211 is fetched to the encoder 202. The first fetched data is '00000000D1D2', and the latch unit 221 composed of 10 deflip-flops Is latched in and is output to a logic operation unit 222 consisting of five exclusive ogates.

The logical operation unit 222 exclusively ORs two 10-bit data latched in the latch unit 221 to obtain five symbol data, which is defined as 'A0, A1, A2, A3, A4'.

If the exclusive OR signal in the prior art is called 'B0, B1, B2', 'A0, A1, A2' has the same input configuration, and 'A3, A4' has the same input configuration as 'A0, A1'. Will have

At this time, 'A0, A1, A2' is generated by '00000000D1' and 'A3, A4' is generated by '0000000D1D2'.

Therefore, when creating symbols of 'C1, C2, C3' with 'A0, A1, A2', 'C4, C5' is generated with 'A4, A5', so the symbol data 'C1, C2, C3, C4' during the first data fetch , C5 'is generated.

The symbol data C1..C5 are B0 (C1), B1 (C2), B2 (C3) and B0 '(C4), B1' (C5), B2 '(C6) obtained by two data inputs in the prior art. ) Corresponds to B0 (C1), B1 (C2), B2 (C3), B0 '(C4), and B1' (C5).

Thereafter, when fetching the second data from the RAM 211 to the encoder 202, data must be input to generate the symbol data C33, C34, and C35 in consideration of the interleaving order, so that the data is fetched to the encoder 202. The data to be generated is 'D11D12 .... D20' to generate symbol data 'C31, C32, C33, C34, C35'.

Accordingly, the 5 * 3 multiplexer 223 selects three symbol data C33, C34, and C35 of the five symbol data C31.. C35 generated by the logic operation unit 222 to the latch unit 224. Will print.

In the case of fetching the third data, the data of 'D22D23 ... D31' is input from the RAM 211 to generate symbol data C64, C65, C66, C67, and C68, and three symbols of the multiplexer 223 are used. When data C65, C66, and C67 are selected, they are latched by the latch unit 224 and stored in the RAM 211.

Thereafter, in the fourth data fetch, data D33D34 ... D42 is fetched from the RAM 211 to generate the symbol data C97, C98, C99, C100, and C101, and symbol data is generated therefrom. Three symbol data C97, C98, and C99 are stored in the RAM 211.

Accordingly, in continuously repeating the above process, while generating symbol data in the encoder 202, the symbol data previously generated from the RAM 211 is output to the outside through the input / output buffer 213 at a constant speed. Outputs symbol data.

In this case, the latch unit 221 is controlled by an AND gate 227 that logically multiplies the clocks CLK2 and CLK3, and the latch unit 224 and the output signal of the inverter 228 which inverts the clock CLK3 and the clock. It is controlled by the AND gate 229 which ANDs the CLK2.

The data fetched from the RAM 211 for encoding is changed according to the frame mode input from the microprocessor 204. The data fetching method according to each mode and three of the five symbols generated therefrom are changed. The operating conditions of the symbol selector 226 for selecting two symbols are as shown in the table of FIG.

For example, when the fetch data Di is 'i <1', all of the data are outputted as '0' at initial execution. Otherwise, the data fetches data from the end of the previous frame to the fetched data.

The symbol selector 226 receives frame mode information from the microprocessor 204, receives an output signal of the 2-bit counter 225, and outputs the symbol selection signals S1 and S2 to the multiplexer 223.

Accordingly, the multiplexer 223 selects and stores three symbol data among the five output signals of the logic calculator 222 in the RAM 211 by the output signals S1 and S2 of the symbol selector 225.

The 2-bit counter 225 is for causing symbol selection in the multiplexer 223 to be repeated at a period of '3'.

The above operation is performed in the same process as the timing diagram of FIG.

Waveform (a) of FIG. 6 is a clock signal for data interleaving as shown in (d) and encoder input as shown in (e) and waveform (b) as shown in FIG. 6 is a clock signal for inputting frame data.

The waveform (c) of FIG. 6 is data output from the flip-flop 205 to the memory block 203 and the waveform (d) of FIG. 6 is interleaved symbol data output from the flip-flop 206.

The waveform (e) of FIG. 6 is fetch data input from the memory block 203 to the latch unit 221, and the waveform (f) of FIG. 6 is encoding input from the second latch unit 224 to the memory block 203. Symbol data.

That is, while the conventional technology interleaves the generated symbols as defined in the IS-95 standard by fetching the frame data according to the frame mode, the present invention fetches and interleaves the frame data in the interleaving order defined in the IS-95 standard. To do.

The present invention needs to perform a virtual symbol repetition function in order to perform a normal operation according to each frame mode, which can be easily solved by examining a power control group specified in the IS-95 standard.

First, when the data rate is full, the repetitive operation for symbol generation is not required otherwise, and the interleaving operation specified in 'IS-95' can be successfully performed by repeatedly performing the above-described process.

In addition, when the data rate is 1/2, 1/4, or 1/8, two, four or eight symbol generation processes are required according to the frame rate after the data is encoded. Even if a power control group with a power is created, each of the individual power control groups is composed of non-overlapping information.

In other words, in the present invention, only the power control group that does not overlap with each data rate is made, and in the case of data rates other than the full rate requiring symbol repetition, the power control group made through the EIP proposed in the present invention is repeatedly outputted. By doing so, the symbol repetition function defined in the IS-95 standard can be performed.

Therefore, the size of the memory required in the present invention is '(size of data frame) * (3 interleaved symbol strings) * 2', which is less than 1/2 of the size of the memory in the prior art.

For example, a conventional CDMA cellular mobile communication system requires about 1152 bits of memory, but in the present invention, 492 bits of memory is sufficient.

As described in detail above, the present invention outputs the frame data stored in the memory in the order to be interleaved and generates the symbol data from the output data, thereby minimizing the use of the memory to 1/2 or less than before, thereby reducing the overall chip size. There is an effect that can be reduced.

Claims (6)

A first latch means for latching frame data, a memory block for storing frame data in the latch means, outputting the interleaved symbol data in an order to be interleaved, and storing the data output from the memory means for a predetermined bit; Generating means for generating two symbols and outputting any number of symbol data to the memory block, second latching means for latching interleaved symbol data outputted from the memory means and transmitting them externally; And means for controlling the encoding of the cellular system. The memory block of claim 1, wherein the memory block stores RAM outputted from the first latching means and outputs the data in an order to be interleaved, and decodes an address under control of a control means. An address decoder which designates a? And an output data of the first latch means to the RAM under control of the control means and an output data of the RAM to the encoding means to output the encoding means. And an input / output buffer which stores a symbol in the RAM and transmits interleaved symbol data output from the RAM to a second latching means. 3. The coding apparatus of a cellular system according to claim 2, wherein the RAM is divided into a frame data storage area and an encoded symbol data storage area. An encoding unit according to claim 1, wherein the encoding means comprises: a first latch unit for latching the 10-bit output data of the memory block, a logical operation unit for exclusively ORing the output data of the latch unit two by two, and outputting five symbol data; A 5 * 3 multiplexer that selects three of the output data of the &lt; RTI ID = 0.0 &gt;, a second latch &lt; / RTI &gt; A symbol selector for outputting the switching signals S1 and S2, a first AND gate for controlling the operation of the first latch unit by ANDing the second and third clocks, and an output signal of the inverter for inverting the third clock. And a second AND gate for performing an AND operation on the second clock to control an operation of the second latch unit. 5. The encoding apparatus of claim 4, wherein the first latch unit comprises ten deflip-flops for respectively latching 10-bit frame data output from the memory block. 5. The encoding apparatus of claim 4, wherein the second latch unit comprises three deflip-flops each latching 3-bit symbol data output from the multiplexer.

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