GB2294616A - Data interleaving process for radio transmission - Google Patents

Abstract

An interleaving process in which data is interleaved or interleaved data is de-interleaved. Input data units are distributed over a plurality of output groups of data units. Thus, in GSM telephony, input bits are distributed over nineteen transmission bursts. Incoming data units are written to a contiguous RAM 1618 and output groups are read from said RAM. Addressing circuitry controls the writing and reading to the RAM, such that data units are stored until required for an output group. After data has been read, these read locations are reused for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process delay for that particular data unit. The addressing circuitry includes modulo counters, each arranged to generate addressing signals for a respective set of memory locations within the RAM. Look-up tables are used to select modulo counts so as to provide conventional addresses to the RAM. The interleaving process is partially effected during the writing of the data into storage, and is completed during the reading of the partially interleaved data from storage. <IMAGE>

Description

INTERLEAVING PROCESS The present invention relates to an interleaving process, consisting of the interleaving of data or the deinterleaving of previously interleaved data.

Radio transmission is subject to short term amplitude variations when the transmitting and receiving antennas are not within direct sight of each other. In this situation, the received signal is the sum of a number of reflected copies of the transmitted signal, each having a different phase. The sum of such randomly phased-shifted signals may vary with time, due to movement of reflecting objects or movement of the transmitting and/or receiving antennas. Amplitude variations resulting from this effect are known as Rayleigh fading.

A further source of interference, particularly in a cellular radio telephony network, results from a large number of users operating on a small number of frequencies which are re-used in different geographical areas known as cells. When a large number of users of such a network are operating simultaneously, it is possible for interference to result from calls made on the same frequency in an adjacent or not-too-distant cell. Interference with radio transmissions may additionally be caused by atmospheric conditions and random electro-magnetic interference caused by certain types of electrical equipment.

When transmitting data using a radio communication link, it is necessary to provide a degree of immunity to such interference, so that for an expected level of interference, errors in data transmission may be correctable at the receiver without undue interruption of data communication.

Data coding consists of adding redundant information to source data in such a way that errors in a received encoded data stream may be identified and corrected. The degree of redundancy which is added determines the number of errors in the received signal which may be corrected, before an uncorrectable level of data interference occurs.

Typical coding methods are characterised by the ability to identify and correct individual bit errors in a data stream. However, these types of coding techniques do not provide resistance to errors which occur in bursts. In order to overcome this difficulty the coded data is interleaved, such that consecutive data bits are spread out in time and interleaved with other data bits which have been delayed from previous parts of the same data signal.

Thus a continuous burst error imposed upon this type of interleaved data signal does not affect contiguous bits from the original data stream, and after de-interleaving the received coded data will have bit errors which are spread out over time and which are correctable using the redundant data which was added at the data coding stage.

Interleaving may be performed to a depth according to the needs of the data signal being sent. Thus data signals which can tolerate an occasional bit error may be interleaved over shorter periods of time than data signals which have a lower error tolerance. Generally, in a digital radio telephony network, speech signals transmitted as data can tolerate an occasional lost uncorrectable bit, whereas data transmitted from a computer over the same radio link, which may be used to convey important information, such as financial data etc., should be transmitted with the least number of possible errors.

In the case of data being transmitted over a radio telephony network from a computer, a greater depth of interleaving may be used. A greater depth of interleaving implies a longer delay time for certain parts of the original data signal before it is actually transmitted.

The delayed data must be stored in a memory or buffer, and the amount of memory used for the process of data interleaving may be great enough to significantly affect the price and power consumption of the equipment in which the interleaving process is to take place. This constraint is particularly applicable to mobile battery powered systems, such as hand-held GSM telephones.

In known systems, interleaving and de-interleaving are achieved by providing a sufficient data memory to store any data bit over the maximum length of time imposed by the interleaving process. However this is wasteful, as the data supplied to the interleaving process is delayed by different times according to its eventual position in the interleaved bit stream output which is eventually transmitted. Thus known systems for interleaving and deinterleaving do not provide the full degree of efficiency which is theoretically implied by the variable timing characteristic of the interleaving or de-interleaving process.

According to a first aspect of the present invention, there is provided a method of performing an interleaving process, wherein input data units are distributed over a plurality of output groups of data units; incoming data units are written to storage means having a plurality of storage locations; output groups of data are read from said storage means; and addressing means control said writing and reading such that data units are stored until required for an output group, whereafter read storage locations are re-used for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process for that particular data unit.

Thus, the present invention provides an advantage in that greater efficiency may be made of the available storage space and storage locations are re-used after data units have been read therefrom. Consequently, the rate at which said storage locations are written to and read from is variable and depends upon the actual interleaving process delay for that particular data unit, rather than the over-all interleaving process depth.

Preferably, a first set of memory locations are read after a first predetermined delay and a second set of memory locations are read after a second predetermined delay. In a preferred embodiment, for transmitting machine-readable data in accordance with the GSM recommendation, a third set of memory locations are read after a third predetermined delay, a fourth set of memory locations are read after a fourth predetermined delay, a fifth set of memory locations are read after a fifth predetermined delay and a sixth set of memory locations are read after a sixth predetermined delay.

According to a second aspect of the present invention, there is provided a method of performing an interleaving process, wherein data is interleaved for radio transmission or interleaved data is de-interleaved after radio transmission, comprising steps of partially performing said interleaving process during the writing of data to a storage means; and completing said interleaving process during the reading of said partially interleaved data from a storage means.

In a preferred embodiment, the data is written to a particular block of storage locations determined by the interleaving process. Thereafter, a plurality of data units may be read from one of said blocks to produce an output burst of data.

In a preferred embodiment, data is stored as multibit words, each consecutive bit is written to a different word and to a different location within said word, to effect a first stage of bit interleaving. Thereafter, a second stage of bit interleaving may be effected when said words are read. Preferably, each of said words contains a number of bits equivalent to the number of bit contributions made to each output burst received from a particular input burst.

The invention will now be described by way of example only, with reference to the accompanying drawings, in which: Figure 1 shows a lap-top personal computer arranged to send data over a mobile radio telephone link, including a GSM cellular phone; Figure 2 details processes operating inside the GSM cellular phone shown in Figure 1 while transmitting data, including an error coding process and an interleaving process; Figure 3 details procedures for implementing the error coding process shown in Figure 2, including a first convolution process and a second convolution process; Figure 4 details a circuit for implementing the first convolution process shown in Figure 3; Figure 5 details a circuit for implementing the second convolution process shown in Figure 3; Figure 6 details a procedure defining a data interleaving scheme of the type shown in Figure 2;; Figure 7 shows a buffer structure for implementing a memory-optimised interleaving process equivalent to the process shown in Figure 6; Figure 8 shows a flow chart for implementing the part of the optimised data interleaving process which writes data bits to the buffer structure shown in Figure 7; Figure 9 shows a flow chart for implementing the part of the optimised data interleaving process which reads bits from the buffer structure shown in Figure 7; Figure 10 shows a first look-up table for facilitating the optimised interleaving process defined in Figures 8 and 9; Figure 11 shows a second look-up table for facilitating the optimised interleaving process shown in Figures 8 and 9; Figure 12 details a read-modify-write process used in the process shown in Figure 8;; Figure 13 shows hardware counters for automatically calculating mathematical expressions shown in Figure 8 and Figure 9; Figure 14 shows a flowchart for implementing the process shown in Figure 8 in an electronic circuit; Figure 15 shows a flowchart for implementing the process shown in Figure 9 in an electronic circuit; Figure 16 details the electronic circuit used for the operations defined in Figure 14 and Figure 15, including a control logic unit; Figure 17 details mathematical operations performed by the control logic unit shown in Figure 16 when performing the interleaving operations shown in Figures 14 and 15; and Figure 18 details mathematical operations performed by the control logic unit shown in Figure 16 when performing de-interleaving operations.

A data communications system is shown in Figure 1, in which a lap-top personal computer 101 is connected to a GSM mobile cellular mobile phone 102 via an interface 103.

The connection to the lap-top personal computer 101 is made via a conventional serial port. The interface 103 provides connections in a form suitable for direct connection to a data port 105 of the cellular telephone 102. Using this arrangement it is possible to provide two-way data communication between the lap-top personal computer 101 and another computer, possibly an officebased computer connected via a modem or similar arrangement to a public switched telephone network.

Operations performed in the cellular telephone 102 shown in Figure 1 for facilitating two-way data communication are detailed in Figure 2. Data supplied to the data port 105 of the cellular telephone 102 is supplied to an error coding process 201. The error coding process introduces additional redundant data bits into the data stream which may be used in a receiver to detect and correct errors resulting from radio interference.

The output from the error coding process 201 is supplied to an interleaving process 202, which interleaves the data across time such that burst errors typical of those encountered in radio communications are translated into dispersed single bit errors after de-interleaving in a receiver, and which may be corrected by suitable error detection software and circuitry. The output from the interleaving processor 202 is supplied to an encryption process 203. The encryption process 203 performs a bitby-bit exclusive-OR operation with a pseudo-random cipher bit stream, such that it is impossible for an unauthorised listener to tune in and decrypt phone calls made using the cellular telephone.

The output from the encryption process 203 is supplied to a burst building process 204, which translates the stream of bits supplied to its input into bursts of a high bit rate and short duration. The purpose of the burst building process 204 is to reduce the time during which the cellular telephone is transmitting. Periods during which transmission does not occur provide time for reception by the receiving circuitry, and communication by other cellular phones in a dynamic time-sharing arrangement. The time-sharing and frequency hopping characteristics used are described in TS GSM 05.02 of The GSM Specifications.

The output of the burst building process 204 is supplied to a radio frequency modulator 205 which modulates a radio frequency carrier wave at a frequency suitable for cellular telephone traffic. The output from the RF modulation process 205 is supplied to the input of a duplexor 206, which performs the function of sharing the antenna 206 between transmission and receiving circuitry.

Reception of data by the cellular telephone is performed using reverse processes corresponding to those just described for transmission. These are radio frequency demodulation 216, burst reduction 215, in which short bursts of high bit data are reduced to a stream of lower bit rate data. Decryption 214 in which a cypher stream identical to the one used to encrypt data is again exclusive-ORed with a pseudo-random cypher bit stream identical to that used for the same data during the encryption process. The result of having passed data through the same exclusive-OR process twice re-creates the original non-encrypted data.

The output of the decryption process 214 is supplied to a de-interleaving process 213 which re-orders the received bits into the order in which they were originally supplied to the interleaving process 202. The output from the de-interleaving process 213 is supplied to an error detection and correction process 212. Provided that the number of errors does not go above a mathematically defined threshold, all errors may be corrected. The error detection and correction process may include reference to a "confidence" measurement for each bit, generated by the radio frequency demodulation process 216, which is used to aid selection of a corrupt bit from a number of candidate corrupt bits identified during the error detection and process. This combination of logical error detection and confidence measurement, followed by error correction, provides a strong immunity to errors.

The output from the error detection and correction process 212 is supplied to the data port 105 of the cellular telephone 102, which communicates received data to the computer 101.

Operations performed for the transmission of data at a rate of 9.6 kbit/s will now be considered in detail.

The error coding process 201 shown in Figure 2 is detailed in Figure 3. Computer data supplied to the error coding process 201 is divided into separate frames each having 240 bits. A 240 bit data frame 301 is supplied to a tailing process 302, which adds 4 bits to the end of the 240 bit frame. Thus a larger frame 303 of 244 bits is generated.

The process of tailing may be described mathematically: the 240 input data bits, labelled d(0) to d(239) are supplied as 240 output bits labelled u(0) to u(240). The final 4 bits in the output series, u(240) to u(243) are set at 0, as these are the tailing bits. The 244 bit data frame 303, containing bits u(0) to u(243), is supplied to a punctured convolutional encoder 304.

A punctured convolutional coder may be considered as having two processes: convolution and puncturing. In practice these processes will usually be performed simultaneously. The convolutional encoding process receives bits u(0) to u(243) from the tailing process 302.

Two similar convolutional processes 305 and 306 operate in parallel to generate a bit stream having twice as many bits as the input bit stream. The outputs from the two convolutional processes 305 and 306 are selected alternately for each bit that is supplied to the convolutional encoder, such that the even output bits C(0), C(2),...,C(486) are supplied by the first convolutional encoding process 305 and the odd output bits C(1), C(3),...,C(487) are supplied by the second convolutional process 306. By increasing the number of bits used to represent data in this way, a corresponding convolutional decoder in the error detection and correction process in a receiver may identify and correct a number of dispersed bit errors.

The bit rate doubling resulting from the convolution process results in a data frame having 488 bits. Widely dispersed occasional bit errors are correctable as a result of the convolutional encoding. Thus a number of bits may be removed from the 488 bits which have been generated, without significantly affecting the performance of the error detection and correction mechanism. Thirty two bits are removed from the 488 bits which have been encoded and these are selected according to a statistical rule, such that the bits which are removed will have the least impact on the efficiency of the error detection and correction mechanism.

Removing bits from a convolutionally encoded data stream in this way is known as "puncturing". The puncturing process is illustrated mathematically as 307 in Figure 3. Thus the punctured convolutional encoder 304 receives data input frames u(0) to u(243) of 244 bits 303 and converts these into output data frames 308 having 456 bits c(0) to c(455).

The first convolutional encoding process 305 shown in Figure 3 is detailed in Figure 4. The convolutional equation 305 shown in Figure 3 may also be written in a form 401, which is more often used when describing a process of this type. The circuit used to implement this operation consists of four individual bit delays (flipflops) 402, 403, 404 and 405, and two exclusive-OR gates 406 and 407. The exclusive-OR operation may be thought of as a binary addition between two bits where the carry operation is not performed.

The circuit in Figure 4 shows an input bit delayed by up to four input bit time periods by the bit delays 402 to 405, so that the current input bit is added to a bit which has been supplied to the input of the circuit three bit periods earlier, and this result is also added to the bit which was supplied four bit periods earlier. The output from the final exclusive-OR gate 407 provides the output from this convolutional process.

In the present application discrete data frames of 244 bits are used, which must not interfere with each other. Thus, the four tail bits added to the original 240 bit frame 301 are used to clear the contents of the single bit delays 402 to 405 progressively at the end of each 244 bit frame supplied to the punctured convolutional encoder 304.

The second convolutional encoding process 306 is detailed in Figure 5. The convolutional equation 306 may also be written in the form 502. The circuit shown in Figure 5 operates in a similar way to that shown in Figure 4, having an additional exclusive-OR gate to add a single delayed bit. In practice the 4 bit delays 402 to 405 and the exclusive-OR gates shown in Figure 4 may also be used for the circuit shown in Figure 5. The output from the convolutional encoding process shown in Figure 4 is labelled GO, and this is alternated with the output from the convolutional process shown in Figure 5, which is labelled G1. Thus 488 bits are generated by alternating data outputs GO and G1 for each input data bit to the punctured convolutional encoder 304.

The interleaving process 202 shown in Figure 2 is detailed in Figure 6. This algorithm is defined in TS GSM 05.03.03 of the GSM Specifications as the type of interleaving which is used for a data channel at the full data rate of 9.6 Kb/s. The algorithm shown in Figure 6 receives input data frames containing 456 bits from the error coding process 201.

Each 456 bit input data frame may be considered as consisting of four 114 bit sub-frames. Each 114 bit subframe is interleaved across the next nineteen transmitted bursts, where each transmitted burst contains 114 bits.

The interleaving process may also be considered as interleaving of each complete 456 bit input data frame over the next twenty-two output bursts; and the reason for this will emerge later in the description.

Line 601 in Figure 6 defines a loop for counting data frames, and each input data frame consists of 456 data bits c(0) to c(455), generated from data supplied by the lap-top personal computer 101. Line 602 defines a loop for selecting a bit position in the current data frame, in the range 0 to 455.

Line 603 calculates the destination burst number B.

Each destination burst contains 114 bits which is a quarter of the length of each input data frame. Thus the expression "4n" is used to provide an offset in the output burst number B, equal to four times the index n of the current input data frame.

The expression "k div 114" adds an offset to the burst number such that the second group of 114 bits in the input data frame, c(114) to c(227), will be interleaved across nineteen bursts beginning with burst number "B+1".

Similarly the expression "k div 114" ensures that the bits c(228) to c(341) in the input data frame are interleaved across nineteen bursts beginning with burst "B+2". The remaining bits c(342) to c(455) are interleaved across nineteen bursts beginning with burst "B+3". Thus it can be seen how interleaving of input sub-blocks of 114 bits across nineteen output bursts may also be considered as interleaving of each 456 bit input data frame across twenty-two output bursts.

The expression "k mod 19" in line 603 selects consecutive destination output bursts for each consecutive input bit. This results in the wide spread of consecutive bits over nineteen bursts, and is thus responsible for defining the major part of the interleaving process of bits across bursts.

The position of a bit in the output burst defined in line 603 is defined in line 604. The value j may take any of the values 0 to 113. The two expressions "k mod 19" and "19 * (k mod 6)" ensure that consecutive bits in the input data frame are widely dispersed across different bit positions in output bursts. The combination of the expressions in lines 603 and 604 results in a complex implementation of the type of interleaving known as diagonal interleaving.

Line 605 defines the end of the loop which starts at line 602 and line 606 defines the end of the loop which begins at line 601. The loop ensures that the operations in lines 603 and 604 are performed 456 times for each input data frame. It can be seen from line 603 that subsequent bits from the input data frame are supplied to different output bursts, and thus are delayed by differing time periods.

In known interleaving schemes, sufficient memory is provided to store input bits for the maximum period corresponding to twenty-two output burst periods. The use of memory in this way is inefficient, as all the data for the previous twenty-two bursts must be stored.

Theoretically it is possible to re-use a memory location as soon as its contents have been read for the current output burst. However, in order to achieve this optimum level of memory usage, it would be necessary to provide a memory addressing scheme which reflects the various time delays required by different bits in the input data frame.

A memory or buffer structure reflecting the time delays required for bits in an input data frame is shown in Figure 7.

The interleaving algorithm shown in Figure 6 results in an interleaving scheme where each input data frame of 456 bits may contribute 6 bits, 12 bits, 18 bits or 24 bits to an output burst. This is because not all of the 114 bit sub-blocks in the input data frame will be interleaved over the next burst. The first 114 bits c(0) to c(113) of an input data frame c(0) to c(455) will contribute 6 bits to the next burst "B", six bits to burst "B+1", six bits to burst "B+2" and six bits to burst "B+3", according to the equation in line 603 of Figure 6.

The second 114 bits c(114) to c(227) will contribute no bits to the next burst "B", six bits to burst "B+1", six bits to burst "B+2", and six bits to burst "B+3". Thus from the current data frame of 456 bits, six bits are supplied to the next burst "B", twelve bits to burst "B+1", eighteen bits to "B+2", twenty-four bits to burst "B+3", twenty four bits to burst "B+4" and so on.

Thus each output burst contains six, twelve, eighteen or twenty-four bits which have been delayed for an integer number of burst periods since it was supplied to the interleaving process as part of a complete data frame.

The structure shown in Figure 7 is divided up into blocks of six bit units, which are shown as squares 701.

Buffer A, 702, contains data which will be used for the next output burst "B". Buffers B, 703, C, 704 and D, 705 contain data which will be used to make up the next three bursts "B+1", "B+2" and "B+3" respectively. In buffer A, 702, each of the nineteen rows, numbered 0 to 18, contains between one and six squares. Each square represents a six bit contribution made by a current or a previous input data frame.

Six bits of data from the first 114 bits c(0) to c(113) of the current input data frame c(0) to c(455) will be interleaved across the next burst "B", and so require no delay. These six bits will be written to the square at row 0 column 0 of buffer A 702. Another six bits from the first 114 bits c(0) to c(113) will be interleaved across burst "B+1", and six bits from the second 114 bits c(114) to c(227) will also be interleaved across burst "B+1".

Thus twelve bits supplied to buffer B 703 require no delay, and these are stored in the two squares at the top of buffer B in row 0; column 0 and row 1, column 0.

Six bits of data from the first 114 bits c(0) to c(113) will be interleaved across burst "B+2", requiring no delay. Six bits from the second 114 bits c(114) to c(227), and six bits from the third 114 bits c(228) to c(341) will also be interleaved across burst "B+2". Thus eighteen bits supplied to buffer C 704 require no delay, and these are represented by the three squares at the top of buffer C 704; in row 0, column 0, row 1, column 0 and row 2, column 0.

Six bits from the first 114 bits c(0) to c(113), six bits from the second 114 bits c(114) to c(227), six bits from the third 114 bits c(228) to c(341) and six bits from the last 114 bits c(342) to c(455) will be interleaved across burst "B+3". Thus twenty-four bits supplied to buffer D 705 require no delay, and these are represented by the four squares at the top of buffer D 705; in row 0, column 0, row 1, column 0, row 2, column 0 and row 3, column 0.

Thus the parts of the current input data frame which are to be supplied to the next 4 bursts are written to parts of buffers A to D 702 to 705 which have a width of one square. Bits from the current input data frame which are to be supplied to bursts "B+4", "B+5", "B+6" or "B+7" are written to parts of buffers A to D which have a width of two squares. Data from the present input frame which is destined for bursts "B+8", "B+9", "B+10" and "B+11" are written to parts of buffers A to D which have a width of three blocks, and so on. Thus the buffer structure shown in Figure 7 provides delays required for complex interleaving of an input data frame over 22 subsequent output bursts.

Buffer A and buffer B have base widths of six blocks, corresponding to a delay of 5 x 4 bursts (4 bursts because there are four burst buffers A to D). Buffer C and buffer D have base widths of five squares, corresponding to a delay of 4 x 4 bursts. Thus buffer A contributes to bursts "B" to "B+20". Buffer B contributes to bursts "B+1" to "B+21", giving the interleaving depth of 22 output bursts. Buffer C contributes data to bursts "B+2" to "B+18". Buffer D 705 contributes data to bursts "B+3" to "B+19".

A row in any of the buffers A to D 702 to 705 which contains more than one square operates as a delay line.

Considering row five in buffer A, once a data bit has been written to the square in column one, which is the middle of the three squares, when the next output burst is read from buffer A, the square in row five which is read from will be the in column two. The next time that row five is written to, the square previously read out in column two will be used. In this way memory is re-used for new data once the delayed data has been transmitted.

Circular counters are used to point to columns, so that after each input data frame has been written to the buffer structure, the circular counters are incremented to point to the next column to be read. Thus the counter for row five may point to column 0, column 1 or column 2, resetting itself automatically to 0 instead of counting beyond two. This type of counter is known as a modulo-3 counter.

The same modulo-3 counter is used to index the column in rows 6, 7 and 8 of buffer A. Furthermore the same modulo-3 counter may be used for rows 6 to 9 in buffer B 703, rows 7 to 10 in buffer C 704 and rows 8 to 11 in buffer D 705. The reason that the same counter may be used for all of these different rows and buffers is that a single read-increment-write cycle is performed once for each input data frame that is interleaved.

A modulo-2 counter is used to index rows 1 to 4 in buffer A, rows 2 to 5 in buffer B, rows 3 to 6 in buffer C and rows 4 to 7 in buffer D. A modulo-4 counter is used to index rows 9 to 12 in buffer A, rows 10 to 13 in buffer B, rows 11 to 14 in buffer C and rows 12 to 15 in buffer D. A modulo-5 counter is used to index rows 13 to 16 in buffer A, rows 14 to 17 in buffer B, rows 15 to 18 in buffer C and rows 16 to 18 in buffer D. A modulo-6 counter is used to index rows 17 and 18 in buffer A and row 18 in buffer B.

A flow chart defining operations for writing an input data frame c(0) to c(455) to buffers A to D is detailed in Figure 8. In process 801 a bit counter k is set to 0. In process 802 the destination buffer is selected by means of a mathematical expression closely related to the one in line 603 in Figure 6. BUFFER is evaluated to a value of between 0 and 3, corresponding to buffers A to D.

Process 803 evaluates the destination row of the selected buffer. Consecutive bits in the input data frame c(0) to c(455) are sent to consecutive rows in buffers indexed by the expression "k mod 19". Process 804 calculates the destination column in the selected buffer.

The destination column is given by the value of the modulo counter used to index the selected row calculated in process 803. There are six modulo counters, these are modulo-1, modulo-2, modulo-3, modulo-4, modulo-5 and modulo-6 (of these, modulo-1 is not a real counter because its output is always zero).

The modulo counter which is used is dependent upon which buffer and which row has been calculated in processes 802 and 803. A look-up table is used so that, for example, row 2 of buffer B will use the modulo-2 counter. The same row in buffer C does not use the same modulo counter, and different look-up tables to determine which of the modulo counters should be used for a given buffer and row combination.

The expression in process 804 identifies which modulo counter contains the column index for the current row.

Process 805 identifies which of the six bits in the square in the row and column is to be written to using the function "k mod 6". This has the effect of sending each consecutive input bits c(k) to different parts of respective six bit words. This adds a small diagonal offset to the bit interleaving process. Further bit interleaving where each six bit word is spread evenly across a 114 bit output burst will be performed when reading from the buffers, is described later on.

Thus in process 806 the next bit c(k) in the input data frame c(0) to c(455) is written to the bit position identified in process 805 at the row and column identified in processes 803 and 804, in the buffer identified in process 802.

In process 807 the bit counter k is incremented. At process 808 the value of k is tested to see if it is greater than 455. If k is less than 455, processes 802 to 807 are repeated. If k is greater than 455 control is diverted to process 809. In process 809 each of the modulo counters: modulo-2, modulo-3, modulo-4, modulo-5 and modulo-6 is incremented. The modulo-1 counter does not need to be incremented as it always has the value of zero.

After process 809 has been completed and all the bits in the current input data frame c(0) to c(455) have been written to the appropriate parts of the buffer structure shown in Figure 7, it is possible to read out bits from the buffer structure in a different order so that the next four bursts "B", "B+1", "B+2", and "B+3" can be generated.

A flowchart for the process of reading four new bursts from the buffer structure is detailed in Figure 9.

In process 901, BUFFER is set to 0 thereby corresponding to buffer A. At process 902, the bit counter k is also set to zero. At process 903 the row in the currently selected buffer is evaluated. At process 904 the column of the next output bit is evaluated. This evaluation is performed in the same way as that described for process 804 in Figure 8, in that a look-up table is used to identify a particular modulo counter which is used for a particular row in a particular buffer.

The value of the selected modulo counter defines the column. Process 905 identifies which bit of the six in the square identified by the row and column calculations in processes 903 and 904 is to be read. This is given by the expression "(k div 19) mod 6". This expression selects bit 0 nineteen times, bit 1 nineteen times, bit 2 nineteen times, bit 3 nineteen times, bit 4 nineteen times and bit 5 nineteen times, with each of the nineteen bits for each bit position being selected from a square in a different row in the current buffer A to D.

For each buffer A to D, there are nineteen squares ready for use as an output burst. The nineteen from buffer A being used for burst "B", the nineteen from buffer B being used for burst "B+1", and so on. Thus, when generating burst "B", one of the squares in each row of buffer A contains six bits for inclusion in burst "B".

However these six bits are from the same quarter of the same data input frame, and thus must be spread out over burst "B" in a regular fashion. Six divides into 114 nineteen times, and this explains the bit interleaving defined by the expression "(k div 19) mod 6" in line 905.

Bit interleaving is thus performed partially when writing to the buffers, and partially when reading from the buffers.

In process 906 the next burst bit is read from the location defined by the BIT, COLUMN, ROW and BUFFER values which have been calculated previously. In process 907 the bit counter k is incremented, and at process 908 the value of k is investigated to see if it is greater than 113. If k is less than or equal to 113, control is returned to process 903 so that calculations for the next bit in the current output burst may be performed. If k is greater than 113 control is diverted to process 909, where the buffer value is incremented. Thus, with an initial BUFFER value of 0, BUFFER will be incremented through 1, 2 and 3, corresponding to buffer B, buffer C and buffer D respectively. In process 901 the value of BUFFER is tested to see if it is greater than 3. If the value of BUFFER is less than or equal to 3, control is returned to process 902, where calculations for generating the next 114 bits of the next output burst begin. If the value of buffer is greater than 3, this indicates that each of the buffers A to D have been used to generate the next 4 bursts, and the interleaving for the next four bursts has been completed.

The look-up table used in process 904 in Figure 9 and process 804 in Figure 8 is detailed in Figure 10. The look-up table is a two-dimensional array, with the first dimension indexed by the buffer number, and the second dimension indexed by the row number. By comparing Figure 10 with the buffer structure shown in Figure 7 it can be seen how the look-up table has been derived. The value in each location of the look-up table shown in Figure 10 determines which of the six modulo counters modulo-l, modulo-2, modulo-3, modulo-4, modulo-5 and modulo-6 is used to generate a value for selecting a column.In the look-up table, a value of zero indicates the modulo-l counter, a value of 1 indicates the modulo-2 counter, a value of 2 indicates the modulo-3 counter, a value of 3 indicates the modulo-4 counter, a value of 4 indicates the modulo-5 counter and a value of 5 indicates the modulo-6 counter.

The buffer structure shown in Figure 7 is addressed by defining a buffer, a row and a column. Real memory is addressed by a single number, rather than the three which have been used so far. A second look-up table is used to translate buffer and row combinations into address offsets in a standard single dimensional memory, to which may be added the output value of the appropriate modulo counter.

A look-up table for translating buffer and row combinations into address offsets is shown in Figure 11.

The offset values may be understood by considering Figure 11 in conjunction with the buffer structure shown in Figure 7. The first offset in buffer A is 0. The second offset, corresponding to the location for the square at row 1, column 0 in buffer A has the value 1. The third offset in buffer A, corresponding to the address of the location for the square at row 2, column 0 in buffer A has the value 3. This structure occurs because one memory location (containing 6 bits) is used for the top square in buffer A, the next row in buffer A contains two squares, and so the offset for the first square in buffer A, which is 1, must have 2 added to it to give the offset for the first square in the second row.

The value of the modulo counter for a row in a particular buffer never increments above a value which would cause its addition to the selected offset value to go beyond or equal to the value of the offset address for the beginning of the next row in that buffer.

Thus the look-up table shown in Figure 11 translates the multi-dimensional buffer structure shown in Figure 7 into single values which are used to address a standard memory circuit with a single dimensional address.

By using a look-up table for memory offsets, an area of memory may be used for interleaving without any unusable or wasted six-bit locations. After each new group of four output bursts is generated, the memory locations from which the four bursts have been read are immediately reused for the next input data frame of 456 bits.

Process 806 shown in Figure 8 requires that a bit in a selected 6 bit word is changed. While it is possible to use memory which has a data bus width of 1 bit, with each bit having a unique memory address, it is preferable to use a data bus width of 6 bits, so that addressing circuitry may be simplified. In order to change a single bit in a multi-bit memory location it is necessary to perform a read-modify-write operation.

The procedure for performing a read-modify-write operation of the type identified in process 806 shown in Figure 8 is detailed in Figure 12. There are three stages for the operation. Firstly, the six bit word 1201 is read from memory, according to the address defined by values which have previously been calculated for the buffer, row and modulo counter value. The selected bit 1202 which is to be written to is then changed to its new value. Finally the modified six bit word 1201 is written back to the memory at the address from which it was initially read.

The read-modify-write operation has the advantage that the address lines to the memory do not change during the operation, so that there is no need to wait for an address line settling time before the final write operation can be performed.

Several of the mathematical expressions used in the flow charts in Figure 8 and Figure 9 may be simplified by using the counter circuits shown in Figure 13. A modulo19 counter 1301 may be used to replace the value calculated by the expression "k mod 19" which occurs several times in the flow charts. The output from the modulo-19 counter 1301 is called MOD-19-COUNT.

The overflow from the modulo-19 counter 1301 occurs each time the modulo-19 counter changes from a value of 18 to 0. This overflow is used to clock a modulo-6 counter 1302, the output of which may replace the expression "(k div 19) mod 6", which is used in line 905 in Figure 9. The output from the modulo-6 counter 1302 is called DIV-19 COUNT, indicating that its value is incremented once for every 19 increments of the modulo-19 counter 1301.

The overflow from the modulo-6 counter occurs every time the modulo-6 counter has an output which changes from 5 to 0, and this overflow is used to clock another counter 1303. The output from the counter 1303 is called DIV-114- COUNT, indicating that it increments once for every 114 increments of the modulo-19 counter 1301. It is used to replace the expression "k div 114", which occurs in process 802 shown in Figure 8 and is used to indicate which of the buffers A to D (indexed by 0 to 3 respectively) is to be used. The output of the counter 1303 may also be used to indicate when the writing (Figure 8) or reading (Figure 9) process has been completed, as it will have been incremented to a value greater than 3 (which does not correspond to any of the buffers A to D).

Another modulo-6 counter 1304 (not the same as the modulo-6 counter which is used to index columns in the buffer structure or the modulo-6 counter 1302 used for generating DIV-19-COUNT values) replaces the expression "k mod 6" which occurs in line 805 in Figure 8. The modulo-6 counter 1304 is incremented at the same time as the modulo-19 counter 1301, and is not part of the cascaded chain of counters 1301, 1302 and 1303. The output of this modulo-6 counter 1304 is called MOD- 6-COUNT.

The flow chart shown in Figure 8 for writing to the buffers shown in Figure 7 may be re-written in the form shown in Figure 14, where locations in a single dimensional RAM address space are used. Furthermore, mathematical expressions have been replaced by the outputs from the counters 1301 to 1304 shown in Figure 13.

Process 1401 re-sets all the counters shown in Figure 13 to zero (the modulo counters used to index columns are not reset at any time). Thus MOD-19-COUNT, DIV-19-COUNT, DIV-114-COUNT and MOD-6-COUNT are all set to zero. In the preferred embodiment, all the counters 1301 to 1304 will automatically reset to a value of zero at this point in the interleaving cycle; process 1401 is included to simplify the explanation. A bit counter, k, is also set to zero in process 1401.

In process 1402 shown in Figure 14 the buffer index is calculated. The buffer value may take any of the values 0 to 3, corresponding to the buffers A to B. The buffer value is given by a combination of MOD-19-COUNT and DIV-114-COUNT. In process 1403 the row is given by MOD19-COUNT. In process 1404 the column is evaluated in the same way as shown in Figure 8, using a look-up table, "MODCOUNT(BUFFER, ROW)", to work out which of the modulo counters is to be used to index the column in the current buffer. In process 1405 an address in random access memory is calculated by adding the column number to the offset value given by the look-up table "OFFSET (BUFFER, ROW)" shown in Figure 11.

Processes 1406, 1407 and 1408 are used to perform a read-modify-write of the type shown in Figure 12. In process 1406 a six bit word at a location defined by the address evaluated in process 1405 is read from random access memory. In process 1407 a bit number is given by the expression MOD-6-COUNT, which indicates the position of the bit which is to be modified in the six bit word which has been read from memory. The bit from the current input frame c(k) is then written to the selected one of the six bits in the word which has been read.

In process 1408 the six bit word containing the updated bit is written back to the same location in memory from which it was read in process 1406. In process 1409 the modulo-19 counter 1301, the modulo-6 counter 1304 and "k" are incremented, resulting in incremented values for MOD-19-COUNT, MOD-6-COUNT and "k", and possible incremented values for DIV-19-COUNT and DIV-114-COUNT.

The modulo-19 counter 1301 will automatically increment the modulo-6 counter giving the value DIV-19-COUNT and the value DIV-114-COUNT when overflow conditions occur.

At process 1410 a comparison is performed to find out whether "k" is greater than 455. If it is not, this indicates that more bits remain in the current input data frame c(0) to c(455) for writing to random access memory.

If "k" is greater than 455, this indicates that all the data bits in the current input frame have been written to random access memory. In process 1411 all the modulo counters, modulo-2, modulo-3, modulo-4 and modulo-6 are incremented. Once this has been done the process of writing to random access memory has been completed.

The processes shown in Figure 9 for reading from buffers and creating the next four output bursts may be re-written as shown in Figure 15. In process 1501 the modulo-19 counters 1301 to 1304 are rest to zero, again this should happen automatically in the preferred embodiment. Thus, initially, MOD-19-COUNT, DIV-19-COUNT, DIV-114-COUNT and MOD-6-COUNT are all zero values. A bit counter "k" is also set to a value of zero.

In process 1502 the buffer index (0 to 3) is given by the value DIV-114-COUNT. In process 1503 the row is given by MOD-19-COUNT. In process 1504 the column is evaluated using look-up tables to determine which of the modulo counters is to be used using the same method as process 1405 shown in Figure 14. In process 1505 an address in random access memory is calculated by adding the column evaluated in process 1504 to an offset value given by the look-up table shown in Figure 11 which is indexed by the buffer number, and the row.

In process 1506 the six bit word at the address in random access memory is read. In process 1507 the position of the bit in the six bit word read in process 1506 is given by DIV-19-COUNT, and this bit is then used for the next output bit in the current burst. In process 1508 the modulo-19 counter 1301 and the modulo-6 counter 1304 are incremented, resulting in incremented values for MOD-19 COUNT and MOD-6-COUNT, and possible incrementations of DIV-19-COUNT and DIV-114-COUNT. In process 1509 a comparison is made to see if k is greater than 455. If it is not, the current series of four output bursts is incomplete and more bits must be read out from random access memory. If "k" is greater than 455, the next four burst have been completed.

A dedicated hardware circuit for implementing the flow charts shown in figures 14 and 15 is shown in Figure 16. The four modulo-counters 1301, 1302, 1303 and 1304 supply values to a control logic unit 1601 which generates a two bit buffer value 1602, defining which of buffers A to D is selected, corresponding to values zero to three respectively. The two bit buffer value 1602 is supplied to the modulo counter look up table "MODCOUNT" 1603 and the random access memory offset look up table "OFFSET" 1604.

The look up tables 1603 and 1604 also receive a five bit value 1605 defining the row of the selected buffer.

The output from the "MODCOUNT" look up table 1603 is supplied to a multiplexer 1606 such that a three bit control value 1607 supplied to the multiplexer 1605 is used to define which output from one of the 6 modulocounters 1608 to 1613 is supplied to the output of the multiplexer 1606.

The output 1614 of the multiplexer 1606 is supplied to a first input of an adder 1607. The second input of the adder 1615 is supplied by the output 1616 from the random access memory look up table "OFFSET" 1604. The output from the adder 1607 defines an eight bit value 1617 in the range 0 to 246 which is used to address a random access memory 1618. The control logic unit 1601 controls operation of the random access memory 1618, such that write or read operations to or from the random access memory 1618 may be performed as appropriate.

Each six bit data word addressed in the random access memory 1618 is supplied to or from a bit manipulation unit 1619. The bit manipulation unit 1619 may select and modify bits in a six bit data word according to control data supplied to it by the control logic unit 1601. Individual bits 1620 may be supplied to or received from the bit input and output of the bit manipulation unit 1619, according to whether the interpolation circuitry is receiving the bit stream from the error coding process 201 or supplying bits to the encryption process 203.

Operations performed by the control logic unit 1601 shown in Figure 16 for calculating BUFFER, ROW and BIT values during the interleaving process are detailed in Figure 17. It can be seen that only a very small amount of arithmetic and multiplexing is required in order to produce the various values required, given the inputs from the modulo counters 1301, 1302, 1303 and 1304. The addition between DIV-114-COUNT and MOD-19-COUNT is an addition between two bit and five bit binary values respectively, with the MOD 4 function being achieved by using only the least significant four bits of the sum. All the other operations are achieved by simple routing of input values through multiplexers to output lines.

The circuit shown in Figure 16 may also be used to perform de-interleaving of data which has been interleaved in the manner which has been described.

When de-interleaving data, at each iteration of the de-interleaving process a complete 456 bit data frame has to be generated from a buffer structure identical to the one shown in Figure 7. Thus a complete data frame has to be generated for every four bursts that are received. A complete data frame will include some data from the current four bursts, but will mostly consist of data from previous bursts.

When considering the initial interleaving process, it was explained that six bits of the input data frame are transmitted in burst "B", twelve bits to burst "B+1", eighteen bits to burst "B+2", twenty-four bits to burst "B+3" and twenty-four bits to most of the remaining bursts "B+4", "B+5" and so on. Thus when receiving and deinterleaving data the delay requirements are the exact reverse of those for interleaving: an inverted form of the buffer structure shown in Figure 7 is required with the longest delays at the top and the shortest delays at the bottom. Such a structure may be implemented using the existing hardware by modifying the expression used to define the row number.

In writing and reading memory during interleaving, the expressions shown in Figure 17 use MOD-19-COUNT to define the row number. If this is changed to "18 - MOD-19 COUNT", as is shown in Figure 18, the required inversion is the result.

Apart from this, the only difference is that MOD-6 COUNT defines the bit position when reading from memory, rather than writing, and that DIV-19-COUNT defines the bit position when writing to memory instead of reading.

In GSM data transmission, bit interleaving and deinterleaving will operate apparently simultaneously, with a very short time delay between the period when one or the other process is being performed. This requires two of the buffer structures shown in Figure 7 for storing data: one for interleaved data, the other for de-interleaved data.

Other elements of the hardware, such as the counters, may be common to both the interleaving and the de-interleaving processes, and single counters may be used to supply the same value to both processes.

In an alternative embodiment it is possible that some or all of the functions described as custom circuitry may be implemented in hardware or software on a semi-custom or off-the-shelf digital signal processor, which may achieve a cost advantage due to the large volume of identical units manufactured.

Claims (35)

1. A method of performing an interleaving process, wherein input data units are distributed over a plurality of output groups of data units; input data units are written to storage means having a plurality of storage locations; output groups of data are read from said storage means; and addressing means control said writing and reading such that data units are stored until required for an output group, whereafter read storage locations are reused for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process delay for that particular data unit.

2. A method according to claim 1, wherein a first set of memory locations are read after a first predetermined delay; and a second set of memory locations are read after a second predetermined delay.

3. A method according to claim 2, wherein a third set of memory locations are read after a third predetermined delay.

4. A method according to claim 2 or claim 3, wherein a fourth set of memory locations are read after a fourth predetermined delay.

5. A method according to any of claims 2 to 4, wherein a fifth set of memory locations are read after a fifth predetermined delay.

6. A method according to any of claims 2 to 5, wherein a sixth set of memory locations are read after a sixth predetermined delay.

7. A method according to any of claims 1 to 6, wherein said storage means is a contiguous array of randomly accessible memory locations, wherein each of said locations is identified by an address.

8. A method according to claim 7, wherein said addresses are generated in response to an output from modulo counting means.

9. A method according to claim 8 when dependent on any of claims 2 to 7, wherein modulo counting means generates respective addresses for each set of memory locations.

10. A method according to claim 8 or claim 9, wherein a particular modulo counting means is selected in response to address signals.

11. A method of performing an interleaving process, wherein data is interleaved for radio transmission or interleaved data is de-interleaved after radio transmission, comprising steps of partially performing said interleaving process during the writing of data to a storage means; and completing said interleaving process during the reading of said partially interleaved data from a storage means.

12. A method according to claim 11, wherein data is written to a particular block of storage locations determined by the interleaving process.

13. A method according to claim 12, wherein a plurality of data units are read from one of said blocks to produce an output burst of data.

14. A method according to any of claims 1 to 13, wherein data is stored as multi-bit words, each consecutive bit is written to a different word and to a different location within said word, to effect a first stage of interleaving.

15. A method according to claim 14, wherein a second stage of interleaving is effected when said words are read.

16. A method according to claim 14 or claim 15, wherein each of said words contains a number of bits equivalent to the number of bit contributions made to each output burst received from a sub-division of an input data frame having the same number of bits as said output burst.

17. A method according to claim 16, wherein each of said words contains six bits.

18. Interleaving apparatus for performing an interleaving process, consisting of the interleaving of data or the de-interleaving of previously interleaved data, wherein input data units are distributed over a plurality of output groups of data units, comprising storage means having a plurality of storage locations; means for writing incoming data units to said storage means; means for reading output groups of data from said storage means; and addressing means for controlling the writing and reading of said data, such that said data units are stored until required for an output group, whereafter read storage locations are re-used for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process delay for that particular data unit.

19. Apparatus according to claim 18, including means for reading a first set of memory locations after a first predetermined delay and means for reading a second set of memory locations after a second predetermined delay.

20. Apparatus according to claim 19, including means for reading a third set of memory locations after a third predetermined delay, reading a fourth set of memory locations after a fourth predetermined delay, reading a fifth set of memory locations after a fifth predetermined delay and reading a sixth set of memory locations after a sixth predetermined delay.

21. Apparatus according to any of claims 18 to 20, including a contiguous array of randomly accessible memory locations, wherein each of said locations is identified by an address.

22. Apparatus according to claim 21, including modulo counting means, wherein said modulo counting means are arranged to generate addressing signals.

23. Apparatus according to claim 22, wherein each modulo counting means generates respective addresses for respective sets of memory locations.

24. Apparatus according to claim 22 or claim 23, including means for generating addressing signals arranged to select an output from a particular modulo counting means.

25. Apparatus according to claim 22, wherein addressing signals are supplied to a look-up table, which in turn selects an output from one of said modulo counting means.

26. Apparatus according to claim 25, wherein addressing signals are supplied to a second look-up table and the output from said second look-up table is combined with the output from said modulo counting means, wherein said combined output provides an address to said storage means.

27. Apparatus for performing an interleaving process, wherein data is interleaved for radio transmission or interleaved data is de-interleaved after radio transmission, comprising means for partially performing said interleaving process during the writing of data to a storage means; and means for completing said interleaving process during the reading of said partial interleaved data from a storage means.

28. Apparatus according to claim 27, including means for writing data within a particular block of storage locations determined by the interleaving process.

29. Apparatus according to claim 28, including means for reading a plurality of data units from one of said blocks to produce an output burst of data.

30. Apparatus according to any of claims 18 to 29, including means for storing data as multi-bit words; means for writing each consecutive bit to a different word and to a different location within said word, so as to effect a first stage of interleaving.

31. Apparatus according to claim 30, wherein a second stage of interleaving is effected when said words are read.

32. Apparatus according to claim 30 or 31, wherein each of said words contains a number of bits equivalent to the number of bit contributions made to each output burst received from a sub-division of an input frame having the same number of bits as said output burst.

33. Apparatus according to claim 32, wherein said storage means is arranged to store six bit words.

34. A method of interleaving or de-interleaving substantially as herein described with reference to the accompanying drawings.

35. Apparatus for effecting interleaving or deinterleaving substantially as herein described with reference to the accompanying drawings.