JPH0951278A - Viterbi decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate semiconductor circuit integration by reducing the circuit scale of a path memory while keeping high speed decoding performance. SOLUTION: A path memory circuit for the Viterbi decoder is configured by memory circuits 21a-21d storing plural steps of path selection signals, trace back circuits 22a-22d tracing back a storage content of the memory circuits based on a maximum likelihood path selection signal, output buffer circuits 24a-24d rearranging outputs of the trace back circuits in a prescribed order, and a trace back control circuit 25. The trace back control circuit 25 operates plural sets of independent circuit operations a-d each employing each of the memory circuits 21a-21d, the trace back circuits 22a-22d, and output buffer circuits 24a-24d alternately for the memory update operation, the trace back operation and the output operation while shifting the phases among the sets a-d.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder that efficiently realizes maximum likelihood decoding of a convolutional code, and more specifically, it is advantageous for integrated circuit integration by greatly reducing the circuit scale of its path memory. Viterbi decoder.

[0002]

2. Description of the Related Art The Viterbi decoding method has been widely adopted in the field of digital transmission and digital recording as an error correction method having a high correction capability. The algorithm is
[1] GDForney, Jr., “The Viterbi Algorithm”,
Proceedings of IEEE, Vol.61, No.3, pp.268-278, Ma
It is described in detail in r.1973.

Before showing the structure of the path memory, the operating principle of the Viterbi decoding method for decoding a convolutional code will be summarized. FIG. 3 shows a configuration example of a convolutional code encoder.
For convenience of explanation, the input side is shown on the right side. The input signals S _i input in series from the right input terminal are sequentially 6 bi
The outputs Y ₁ and Y _{2 of} the exclusive OR circuit are output to the output terminal on the left side as convolutional codes while being taken into the shift register of t. The constraint length of this encoder is K =
7, the coding rate is R = 1/2, and the number of states is Ns = 64. The Viterbi decoding operation is based on the received code,
State S = {S ₅ , determined by the contents of the register of this encoder,
It is equivalent to estimating the transitions of S ₄ , S ₃ , S ₂ , S ₁ , S ₀ }. If the state S is the state of FIG. 3 at time t−1, then at the next time t, {S ₄ , S ₃ , S ₂ ,
S ₁ , S ₀ , S _-1 }.

In the case of the encoder having the configuration shown in FIG. 3, focusing on the shift-out bit and the shift-in bit of the register,
Register state transitions occur between one set of states and another. This is shown in FIG. Considering mainly the set of states at the transition destination, 64 states S each consisting of 6 bits are represented by a decimal number and divided into cases represented by odd numbers (m) and even numbers (n). Then, as shown in FIG. 4, the transition source (i or j) and the transition destination (m or n) can be associated with each other. In the following description,
It is assumed that "x >>1" indicates the number obtained by shifting x to the LSB side by 1 bit, and "x ^ y" indicates the number of results of the exclusive OR operation of each bit of x and y.

In Viterbi decoding, candidates for a decoding path are sequentially truncated based on a path metric corresponding to each state so that only decoding paths (surviving paths) corresponding to the number of states (Ns) are left. To do. By doing so, efficient maximum likelihood decoding can be realized. As shown in FIG. 5, each of the surviving paths has a higher probability of merging into one path corresponding to the past than a certain suitable length (Ms). The information bit δ (t−Ms) corresponding to the transition traced back by Ms stages of the path having the smallest path metric (maximum likelihood path) among the surviving paths becomes the Viterbi decoding output.

The update of the path metrics Γ _t ^{(n )} and Γ _t ^(m) of the transition destination states n and m when the time shifts from t−1 to t is performed by the following equation in the set of state transitions shown in FIG. This is performed as in (1) and (2).

[0007]

Γ _t ⁽ⁿ⁾ = min {Γ _t-1 ⁽ⁱ⁾ + λ _t (ν), Γ _t-1 ^(j) + λ _t (ν ')} ... (1) Γ _t ^(m) = min {Γ _t-1 ⁽ⁱ⁾ + λ _t (ν '), Γ _t-1 ^(j) + λ _t (ν)} ... (2) where ν and ν'are called branch codes, and state (i),
It corresponds to each coded bit (Y ₁ Y ₀ ) at the time of transition from (j) to (m) and (n), and ν ′ = ν̂ (11). The branch metrics λ (ν) and λ (ν ′) are
It corresponds to the error (distance) of the demodulated data (after depuncturing) corresponding to each branch code, and four are generated at each decoding step. For example, 0 to 7 when expressed in 3 bits
Takes the value of. Each state transition set (Ns / 2 = 32 sets)
Then, the path metric is calculated using either λ (00) and λ (11) or λ (01) and λ (10).

Simultaneously with the calculation of the path metric, the selection flags β _t ⁽ⁿ⁾ and β _t ^(m) indicating which state has transited to the states n and m are set by, for example, the following equations (3) and (4). ) Occurs under the conditions shown in.

[0009]

When Γ _t-1 ⁽ⁱ⁾ + λ _t (ν) <Γ _t-1 ^(j) + λ _t (ν ′), β _t ⁽ⁿ⁾ = 0, Γ _t-1 ⁽ⁱ⁾ + λ _t ( When ν) ≧ Γ _t-1 ^(j) + λ _t (ν ') β _t ⁽ⁿ⁾ = 1 (3) Γ _t-1 ⁽ⁱ⁾ + λ _t (ν') <Γ _t-1 ^(j) When + λ _t (ν), β _t ^(m) = 0, Γ _t-1 ⁽ⁱ⁾ + λ _t (ν ') ≧ Γ _t-1 ^(j) + λ _t (ν), β _t ^(m) = 1 (4) These are used in updating survivor paths, which will be described later. formula
The operations (1) to (4) are executed by an addition / comparison / selection unit (hereinafter abbreviated as ACSU). The circuit configuration is shown in FIG.

Based on each selection flag, the candidate of the decoding path (surviving path) to be left in each state is updated as shown in the following equations (5) and (6) (when information bits are left, Called direct realization).

[0011]

When β _t ⁽ⁿ⁾ = 0, V _t ⁽ⁿ⁾ = {0, v _t-1 ^{(i, 0)} , v _t-1 ^{(i, 1)} , ..., V _t-1 ^{(i , Ms-1)} }, when β _t ⁽ⁿ⁾ = 1 V _t ⁽ⁿ⁾ = {0, v _t-1 ^{(j, 0)} , v _t-1 ^{(j, 1)} , ..., v _{t- 1} ^{(j, Ms-1)} } (5) When β _t ^(m) = 0 V _t ^(m) = {1, v _t-1 ^{(i, 0)} , v _t-1 ^{(i, 1)} , ..., v _t-1 ^{(i, Ms-1)} }, when β _t ^(m) = 1 V _t ^(m) = {1, v _t-1 ^{(j, 0)} , v _t-1 ^{(j , 1)} , ..., v _t-1 ^{(j, Ms-1)} } (6) where v _t ^{(S, k)} is k steps from the present of the surviving path corresponding to state S at time t. Dating back (time t
Information bits (corresponding to -k). In addition, M in state S
The surviving path of s stages is given by the following expression (7).

[0012]

V _t ^(S) = {v _t ^{(S, 0)} , v _t ^{(S, 1)} , v _t ^{(S, 2)} , ..., V _t ^{(S, Ms)} } where S is an even number When v _t ^{(S, 0)} = 0, and S is an odd number v _t ^{(S, 0)} = 1 (7) In addition, the right side (v ^{(S, Ms)} ) of each surviving path is the oldest information. Equivalent to a bit.

Among the survivor paths, the survivor path having the smallest path metric corresponding to each survivor path is the maximum likelihood path, and the Viterbi decoding output _Δt is determined by the following equation (8).

[0014]

[Number 5] _{Δ t = δ (t-Ms} ) = v t (SL, Ms) ... (8) here,

## EQU6 ## Γ _t ^(SL) = min {Γ _t ⁽⁰⁾ , Γ _t ⁽¹⁾ , Γ _t ⁽²⁾ ,…, Γ _t ^(Ns-1) } (9), and the state SL is The state (maximum likelihood path information) corresponding to the maximum likelihood path is shown.

A conventional path memory circuit which realizes the operations corresponding to the above equations (5) to (8) has a configuration as shown in FIG.
The signal on the input side of each register (flip-flop) is the information bit of the surviving path corresponding to time t, and the signal on the output side is the information bit of the surviving path corresponding to time t-1. Viterbi decoding output, the maximum likelihood path information S _L, v by ^{_{t t (0, Ms) ~v}} t (Ns, Ms) so obtained by selecting one of, can be realized by the configuration of the selector of FIG.

To realize high-speed (for example, several + Mbps or more) Viterbi decoding by a method of leaving information bits, Ns / 2 is required.
For the set of state transitions of = 32, it is necessary to update the path memory (= surviving path) at once in one step = 1 clock as shown in the equations (5) and (6). For this reason, it is impossible to configure the path memory with the RAM, and when configuring the path memory of FIG. 7, Ms × 64 selectors and (Ms −1) × 64 registers (flip-flops) are required. Become.

[0017]

In order to realize the Viterbi decoding corresponding to the punctured code with the code rate R = 7/8, in which the convolutional code with the number of states 64 is the mother code, the path memory must be It is necessary to set the number of rounds Ms to about 100 (Reference [2], Yasuda, Hirata, and Ogawa, "High-code-rate convolutional codes with easy Viterbi decoding and their characteristics", Theological Theory (B), Vol. See J64-B, No7, pp.573-580, Jul.1981.).

According to the configuration of FIG. 7, for example, 100 × 64 selectors and 99 × are used to configure the path memory.
64 registers are required, and if the number of gates per selector is 3 and the number of gates per register (flip-flop) is 5, the total is about 50 k gates, and the circuit scale is large and it is difficult to form an IC. It was

An effective way to reduce this path memory is:
This is to configure the register with a RAM having a higher degree of integration. However, updating the contents of the path memory by the method described above requires the number of data buses as registers, which is not realistic. When integrated into an IC, the number of wirings becomes enormous, and the chip size does not decrease in the end.

A method in which a RAM can be used as a path memory,
There is a traceback method. This is from [3] CM, Rader,
"Management in a Viterbi Decoder", IEEE Trans.
on Commun., Vol.COM-29, No.9, pp.1399-1401, Sep.19
Details on 81. In the traceback method, a selection flag for each decoding step (time) is stored in a path memory, and the state transition corresponding to the maximum likelihood path at time _t from the state S _{L, t} to Ms stages is traced back to perform Viterbi. Decoding output δ
This is a method of obtaining (t-Ms). Traceback is shown in Figure 9.
It can be realized with the circuit configuration of. However, simply performing this traceback at each decoding step cannot realize a high-speed (several + Mbps) decoding rate.

In view of the above problems, it is an object of the present invention to provide a Viterbi decoder in which the circuit scale of the path memory is reduced and which can be easily integrated into a semiconductor integrated circuit while maintaining high-speed decoding performance.

[0022]

According to a first aspect of the present invention for solving the above-mentioned problems, a branch metric operation circuit for calculating a branch metric which is a quantity indicating the certainty of a branch of a state transition, and a branch metric operation circuit for each state are provided. An addition / comparison / selection circuit that calculates a path metric and outputs a path selection signal that indicates which path is selected, and a maximum output that outputs a maximum likelihood path selection signal by selecting the maximum likelihood path from the path metrics for each state. In a Viterbi decoder configured to include a likelihood determination circuit and a path memory circuit that stores and holds a path that is a candidate for decoding, the path memory circuit includes a memory circuit that holds the path selection signal for a plurality of steps, A traceback circuit for tracing back the stored contents of the memory circuit based on the maximum likelihood path selection signal, and a predetermined output of the traceback circuit An output buffer circuit that is rearranged in order, and a traceback control circuit, and a plurality of sets of the memory circuit, the traceback circuit, and the output buffer circuit that are operable independently of each other are provided, and the traceback control circuit is The summary is that the path memory updating operation, the traceback operation, and the output operation of each group are alternately operated by shifting the phase between the groups.

According to the first invention of the present application, a plurality of sets each including a memory circuit, a traceback circuit, and an output buffer circuit are provided, so that the path memory update operation, the traceback operation, and the decoded data while tracing back are performed. Can be alternately operated in a plurality of sets. As a result, the path memory can be configured with RAM to reduce the circuit scale, and while one group performs traceback and output operations simultaneously in parallel while the path memory is being updated, continuous and high-speed operation is possible. Viterbi decoding can be realized.

In the second invention of the present application, a branch metric calculation circuit for calculating a branch metric which is a quantity indicating the certainty of a branch of a state transition, a path metric for each state, and which path is selected. The addition / comparison / selection circuit that outputs a path selection signal that indicates whether or not the maximum likelihood path selection signal that outputs the maximum likelihood path selection signal from the path metric for each state, and the path that is a candidate for decoding In a Viterbi decoder configured to store and hold a path memory circuit that holds the path selection signal for a plurality of steps, and the memory based on the maximum likelihood path selection signal. A traceback circuit that traces back the stored contents of the circuit,
An output buffer circuit for rearranging the output of the traceback circuit in a predetermined order; and a traceback control circuit, comprising a plurality of sets of the memory circuit and the traceback circuit, which are operable independently of each other, The back control circuit causes the path memory update operation, the trace back operation, and the output operation of each set to be alternately operated by shifting the phase between each set, and the output buffer circuit outputs the output of each trace back circuit. The gist is to multiplex and rearrange in a predetermined order.

In the second invention of the present application, a path memory update operation, a traceback operation, and an output operation for outputting decoded data while tracing back are alternately operated in a plurality of groups, and an output buffer is provided for each decoding. It is possible to input while switching the data output, rearrange in a predetermined order, and output. As a result, the path memory can be configured with RAM to reduce the circuit scale, and while one group performs traceback and output operations simultaneously in parallel while the path memory is being updated, continuous and high-speed operation is possible. Viterbi decoding can be realized.

Further, in the present invention, four sets of the memory circuits can be provided. Further, in the present invention, two sets of the memory circuits capable of the read modify write operation can be provided. In addition, the present invention may include three sets of the memory circuits.
Further, in the present invention, the traceback circuit can be time-shared by a plurality of sets.

[0027]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a Viterbi decoder according to the present invention.
In the figure, the Viterbi decoder includes a phase synchronization circuit 10,
Depuncture circuit 11 and BMU (Branch Metric Uni
t) 12, a normalization circuit 13, an ACSU 14, a maximum likelihood determination section 15, and an Ms stage path memory 20.

The Ms stage path memory 20 includes four sets of RAMs 21a to 21d each having 64 bits × (2 × Ms) stages.
, Four traceback circuits 22a to 22d, a selector 23a that selects the outputs of the traceback circuits 22a and 22c, a selector 23b that selects the outputs of the traceback circuits 22b and 22d, and a selector 23a. The buffer A (24a) that rearranges the output of the traceback circuit selected in step 1 in the order of last-in first-out (hereinafter abbreviated as LIFO) and the output of the traceback circuit selected by the selector 23b in the order of LIFO. A buffer B (24b) which is rearranged by the above, and a selector 26 which selects the output of the buffer A or the buffer B as a Viterbi decoding output,
And a traceback control circuit 25.

Next, the operation of this embodiment will be described. The soft-decision data (demodulated data Id, Qd) is phase-locked by the phase-locking circuit 10, and then the depuncture circuit 1
1 performs depuncture processing corresponding to the puncture processing on the transmission side, and the BMU 12 calculates a branch metric. Next, after the normalization processing by the normalization circuit 13 for preventing the overflow of the path metric, the ACSU 14 (the configuration shown in FIG.
The path metric is updated in (preparation). Among the respective path metrics, the maximum likelihood path metric Γ L (usually the minimum value) corresponding to the maximum likelihood path is judged by the maximum likelihood judging section 15, and this is used for the normalization.

The value of this maximum likelihood path metric Γ L tends to increase when the rates of phase synchronization and puncture do not match. Therefore, this synchronization determination is performed and appropriate phase and depuncture processing is selected. .

The Ms-stage path memory circuit 20 stores and holds the required number of Viterbi decoding candidates (Ms stages).
To update this content, select flag β ⁽⁰⁾ corresponding to each state
~ Β ⁽⁶³⁾ and maximum likelihood path information corresponding to the maximum likelihood path are used. Note that the maximum likelihood path information is not necessarily required if it is possible to store and hold the number of stages sufficiently larger than the required number of stages.

The key point for realizing a decoding rate of several tens of Mbps using the traceback method is that the survivor path is
It uses a very clear and simple principle that when all the survivors join together when going back up, they also join one beyond (dashed line in Fig. 5). That is.

For example, 2 × Ms stages are prepared as a memory circuit, and one cycle of traceback is set to 2 × Ms steps. From the above principle, once Ms stages of traceback are performed, subsequent tracebacks can successively obtain decoded outputs (correct within the correction capability of Viterbi decoding). register contents S _{r, k} after traceback of k steps,

## _EQU00007 ## Let S _{r, k} = β _tk ^{(Sr, k-1)} ^ (S _{r, k-1} >> 1) (10). Here, S _{r, 0} = S _{L, t} . Then, the Viterbi decoding output becomes valid in the range of Ms ≤ k ≤ 2 × Ms,

(8) δ (t−k) = S _{r, k} ^ 1 (11) However, since they are played in the reverse order in terms of time,
An output buffer having a LIFO function is provided to output in the correct order. As the output buffer, for example, a memory of 1 bit × Ms word or a shift register capable of left / right shift may be used. In this way, the Viterbi decoded output can be obtained with Ms bits by one traceback.

To perform Viterbi decoding continuously, 2 × Ms
Four sets of the memory circuits 21 of the stages and the traceback circuit 22 of FIG. 9 are prepared respectively a to d, are operated with a time difference, and the respective decoded outputs are switched by the selectors 23a and 23b and used. FIG. 10 shows a timing chart for explaining the operation. The reason why four sets are prepared instead of two sets is that only one half of the one reading cycle of the RAM directly contributes to the output.

In the timing chart of FIG. 10, it is assumed that a sufficiently long code sequence is subjected to Viterbi decoding and a path selection flag β composed of 64 bits is output from ACSU at each clock. As a result, the state of the path selection flag β _t changes with each clock, but the operation delimiter (phase) of this embodiment is provided by the Ms path selection flags β _t in time series.

First, RAMa and traceback circuit a
The operation of group a consisting of will be described. The RAMa stores 2Ms path selection flags β _{0 to} β _2Ms-1 in each memory address in the ascending order of address in the first 2Ms clock period. Then, during the next Ms clock period, the path selection flags β _{2Ms-1 to} β _Ms are read from the RAMa in the descending order of address, and are traced back by the traceback circuit a (TBa). "TB" of the traceback circuit indicates a cycle that is not output (invalid) only by the traceback operation.

Next, during the next Ms clock period, RA
The path selection flags β _{Ms-1 to} β ₀ are read from Ma in the address descending order, traceback is performed by the traceback circuit a, and valid Ms traceback outputs are output (OUTa), and also via the selector 23a. Are sequentially written in the buffer A.

Next, during the next Ms clock period, the traceback data is read from the buffer A in the reverse order (LIFO) from the order in which it was written, and is output as a Viterbi decoded output via the selector 26.

Next, RAMb and traceback circuit b
The operation of group b will be described. The operation of group b is
The phase is delayed by Ms clocks from the operation of group a. That is, writing to RAMb is started with a delay of Ms clocks from the start of writing to RAMa, and 2Ms path selection flags β _{Ms to} β _3Ms-1 are sequentially stored in the respective storage addresses in ascending order of addresses during a period of 2 _Ms clocks. And next Ms
During the clock period, the path selection flag β is output from the RAMb.
_{3Ms-1 ~β 2Ms} is read at the address descending order, it is traced back by the trace-back circuit b (TBb).

Next, during the next Ms clock period, RA
The path selection flags β _{2Ms-1 to} β _Ms are read from Mb in the address descending order, traceback is performed by the traceback circuit b, and valid Ms traceback outputs are output (OUTb) and also via the selector 23b. Are sequentially written in the buffer B.

Next, during the next Ms clock period, the traceback data is read from the buffer B in the reverse order (LIFO) from the order in which it was written, and is output as a Viterbi decoding output via the selector 26.

Similarly, the operation of the c set consisting of the RAMc and the traceback circuit c is delayed in phase by Ms clocks from the operation of the b set, but the buffer used is the buffer A. Similarly, the operation of the d set consisting of the RAMd and the traceback circuit d is delayed in phase by Ms clocks from the operation of the c set, but the buffer used is the buffer B.

In this way, the buffers A,
The buffer B is shared by the b group and the d group and rearranged so that the Viterbi decoding output without interruption, OUTa, OUTb, OUTc, OUT is output from the selector 26.
d is obtained.

It was also confirmed by circuit operation simulation by a computer that Viterbi decoding can be continuously performed with this configuration. FIG. 11 shows the simulation result and the theoretical upper bound characteristic of the bit error rate (BER) of the Viterbi decoder according to the above-mentioned document [2]. As shown in FIG. 1, the output buffer may be shared among a plurality of RAMs for time-division operation, or like the second embodiment shown in FIG. Alternatively, the selector 26 may be provided for each output and the output after the rearrangement may be selected by the selector 26.

When the RAM access speed has a margin and double-rate access of read-modify-write is possible, read-write for traceback and write for update of path memory can be performed by read-modify-write. Therefore, RAMa, RAMc, RA
Mb and RAMd are common to each other and can be realized by two sets of RAM circuits.

The circuit scale of the path memory composed of four sets of memory circuits is about 0.2 assuming that a synchronous RAM is adopted.
From gate / bit, (64bit x (2 x Ms) word)
× 4 = 49k bits corresponds to about 9.8k gates. About 35k gates can be realized in the entire Viterbi decoding (Ms = 96,
Corresponds to punctured codes up to R = 7/8). The actual configuration of the path memory is, for example, 16-bit × 192-word RA
The configuration uses 16 M / ICs.

Next, a third embodiment of the present invention will be described. In reducing the circuit scale, the chip size of an IC has a large number of wirings or a large chip area for accommodating wirings, as well as the number of gates. Reducing the number (or the number of data) of the RAM rather than minimizing the number of bits of the RAM may reduce the number of wirings and the total length of wirings, which may be advantageous for circuit miniaturization.

In consideration of this point, FIG. 12 shows a block diagram in the case where the path memory is composed of three sets of memory circuits, and FIG. 13 shows its operation timing, as a third embodiment of the present invention.

In FIG. 12, the Ms stage path memory 40
Are three sets of memory circuit RAMs 21a to 21c of 64 bits × (3 × Ms) stages, three traceback circuits 22a to 22c, and traceback circuit 2 respectively.
Selectors 23a and 23b for selecting outputs 2a to 22c
And a buffer A that rearranges the outputs of the traceback circuits selected by the selectors 23a and 23b in the order of LIFO.
(24a), buffer B (24b), and buffer A (2
4a) or the output of the buffer B (24b) to select a Viterbi decoding output, and a traceback control circuit 25.

Each memory circuit RAM 21a-21c has 3
As a × Ms stage, a decoded output of 2 × Ms bits is obtained by one traceback. The total number of bits in RAM is 5 in total of 3 sets
5k bits (corresponding to 11k gates), but the number of wires is 3
/ 4 (for example, 16bit × 288word RAM / I
It can be configured by using 12 Cs (arranged in 4 × 3). The delay amount from the input of the demodulated data to the output of the Viterbi decoding is 4 × Ms (bit time) to 6 × Ms.
(Bit time), but it does not matter so much when the decoding rate is high.

Further, as a modified example of this embodiment, the traceback circuit can also be shared in a time division manner. For example, according to the timing diagram of FIG.
Since a and 22c do not perform traceback processing at the same time, they can be shared. Similarly, 22b and 22d can be shared.

In the above description of the embodiment, the initial value S _{r, 0} of the traceback is the state S corresponding to the maximum likelihood path.
_{Although L, t} is set, S _{r, 0} can be set to an arbitrary value (for example, state (0)) if the number Ms of traceback steps is sufficiently large.

In the above embodiment, the configuration of Viterbi decoding has been shown by taking the convolutional coding which is a non-systematic code shown in FIG. 3 as an example. However, any convolutional code including a systematic code is shown. It is clear that the present invention is effective for a Viterbi decoder with respect to encoding.

[0054]

As described above, according to the present invention, the path memory can be constituted by the RAM while enabling the high speed operation, so that there is an effect that the circuit scale of the high speed operation Viterbi decoder can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a Viterbi decoder according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of a Viterbi decoder according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a convolutional code encoder.

FIG. 4 is a state transition diagram showing a set of state transitions.

FIG. 5 is an explanatory diagram of a survival path.

FIG. 6 is a block diagram showing a configuration of an addition comparison selection unit (ACSU).

FIG. 7 is a block diagram showing a direct implementation of a conventional path memory.

FIG. 8 is a block diagram showing decoded output by maximum likelihood path selection.

FIG. 9 is a block diagram showing a configuration of a traceback circuit.

FIG. 10 is a first timing chart showing a decoding operation by traceback.

FIG. 11 is a graph showing a decoded BER characteristic by traceback.

FIG. 12 is a block diagram showing the configuration of a third embodiment of a Viterbi decoder according to the present invention.

FIG. 13 is a second timing chart showing the decoding operation by traceback.

[Explanation of symbols]

10 Phase synchronization circuit 11 Depuncture circuit 1
2 BMU 13 normalization circuit 14 ACSU
15 maximum likelihood determination circuit 16 synchronization determination circuit 21a, 21b, 21c, 21d RAM 22a,
22b, 22c, 22d Traceback circuit 24
a, 24b, 24c, 24d buffer 25 traceback control circuit 26 selector
30 Ms stage path memory

Claims (6)

[Claims] 1. A branch metric calculation circuit for calculating a branch metric, which is a quantity indicating a certainty of a branch of a state transition, and a path selection signal for calculating a path metric for each state and indicating which path is selected. , A maximum likelihood determination circuit that selects the maximum likelihood path from the path metric for each state and outputs a maximum likelihood path selection signal, and a path memory circuit that stores and holds a path that is a candidate for decoding. In the Viterbi decoder configured with, the path memory circuit traces back the stored contents of the memory circuit based on the maximum likelihood path selection signal, and a memory circuit that holds the path selection signal for a plurality of steps. Traceback circuit, an output buffer circuit for rearranging the output of the traceback circuit in a predetermined order, and a traceback control A plurality of sets of the memory circuit, the traceback circuit, and the output buffer circuit that can operate independently of each other, and the traceback control circuit includes a path memory update operation for each set and a trace A Viterbi decoder characterized in that the back operation and the output operation are alternately operated by shifting the phase between each pair. 2. A branch metric calculation circuit for calculating a branch metric, which is a quantity indicating a certainty of a branch of a state transition, and a path selection signal for calculating a path metric for each state and indicating which path is selected. , A maximum likelihood determination circuit that selects the maximum likelihood path from the path metric for each state and outputs a maximum likelihood path selection signal, and a path memory circuit that stores and holds a path that is a candidate for decoding. In the Viterbi decoder configured with, the path memory circuit traces back the stored contents of the memory circuit based on the maximum likelihood path selection signal, and a memory circuit that holds the path selection signal for a plurality of steps. Traceback circuit, an output buffer circuit for rearranging the output of the traceback circuit in a predetermined order, and a traceback control And a plurality of sets of the memory circuit and the traceback circuit that are operable independently of each other, wherein the traceback control circuit includes a path memory update operation, a traceback operation, and an output of each set. A Viterbi decoder characterized in that the operation and the operation are alternately performed by shifting the phases between the sets, and the output buffer circuit multiplexes the outputs of the traceback circuits and rearranges them in a predetermined order. 3. The Viterbi decoder according to claim 1, further comprising four sets of the memory circuit. 4. The memory device according to claim 1, further comprising two sets of the memory circuits capable of a read modify write operation.
Alternatively, the Viterbi decoder according to claim 2. 5. The Viterbi decoder according to claim 1, further comprising three sets of the memory circuit. 6. The Viterbi decoder according to claim 1, wherein the traceback circuit is shared by a plurality of sets in a time division manner.