EP0918292A3 - Minimum and maximum value searching method - Google Patents

Minimum and maximum value searching method Download PDF

Info

Publication number
EP0918292A3
EP0918292A3 EP98309348A EP98309348A EP0918292A3 EP 0918292 A3 EP0918292 A3 EP 0918292A3 EP 98309348 A EP98309348 A EP 98309348A EP 98309348 A EP98309348 A EP 98309348A EP 0918292 A3 EP0918292 A3 EP 0918292A3
Authority
EP
European Patent Office
Prior art keywords
value
selector
predetermined value
extremum
count
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98309348A
Other languages
German (de)
French (fr)
Other versions
EP0918292A2 (en
Inventor
Mohammad Shafiul Mobin
Sivanand Simanapalli
Larry R. Tate
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia of America Corp
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Publication of EP0918292A2 publication Critical patent/EP0918292A2/en
Publication of EP0918292A3 publication Critical patent/EP0918292A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation

Abstract

The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register (100) is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit (26) and a multiplexer (92). The value from the group and the predetermined value are compared in the arithmetic logic unit (26). A selector (88) is set to one of a first or second logic state. In the first logic state the selector (88) selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag (84) set by the comparison in the arithmetic logic unit (26) and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector (88) is set to a first state and the value is less than the predetermined value. The predetermined value is replaced with the extremum and the count register count is stored when the selector (88) is set to the second state and the value is greater than the predetermined value.
EP98309348A 1997-11-24 1998-11-17 Minimum and maximum value searching method Withdrawn EP0918292A3 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US6669397P 1997-11-24 1997-11-24
US66693P 1997-11-24
US09/074,669 US6272188B1 (en) 1997-11-24 1998-05-08 Single-cycle accelerator for extremun state search
US74669 1998-05-08

Publications (2)

Publication Number Publication Date
EP0918292A2 EP0918292A2 (en) 1999-05-26
EP0918292A3 true EP0918292A3 (en) 2000-03-01

Family

ID=26747052

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98309348A Withdrawn EP0918292A3 (en) 1997-11-24 1998-11-17 Minimum and maximum value searching method

Country Status (2)

Country Link
US (1) US6272188B1 (en)
EP (1) EP0918292A3 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6848074B2 (en) 2001-06-21 2005-01-25 Arc International Method and apparatus for implementing a single cycle operation in a data processing system
DE10163700A1 (en) * 2001-12-21 2003-07-10 Systemonic Ag Procedure for determining a maximum or minimum
WO2004066141A2 (en) * 2003-01-15 2004-08-05 Globespanvirata Incorporated Apparatus and method for determining extreme values
US7424698B2 (en) * 2004-02-27 2008-09-09 Intel Corporation Allocation of combined or separate data and control planes
US20050223110A1 (en) * 2004-03-30 2005-10-06 Intel Corporation Heterogeneous building block scalability
US20060004902A1 (en) * 2004-06-30 2006-01-05 Siva Simanapalli Reconfigurable circuit with programmable split adder
US8285765B2 (en) * 2006-12-11 2012-10-09 International Business Machines Corporation System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences
KR20100085131A (en) * 2007-10-26 2010-07-28 콸콤 인코포레이티드 Optimized viterbi decoder and gnss receiver
WO2013009697A1 (en) * 2011-07-08 2013-01-17 Bendix Commercial Vehicle Systems Llc Image-based vehicle detection and distance measuring method and apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4578800A (en) * 1982-07-12 1986-03-25 Yutaka Yasuda Synchronization circuit for a Viterbi decoder
WO1995009391A1 (en) * 1993-09-27 1995-04-06 Ntt Mobile Communications Network Inc. Minimum value/maximum value retrieving apparatus
JPH0951278A (en) * 1995-08-08 1997-02-18 Toshiba Corp Viterbi decoder

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0656712A1 (en) * 1993-11-16 1995-06-07 AT&T Corp. Viterbi equaliser using variable length tracebacks
US6009128A (en) * 1997-09-08 1999-12-28 Lucent Technologies, Inc. Metric acceleration on dual MAC processor
EP0901234A3 (en) * 1997-09-08 2004-06-16 Lucent Technologies Inc. Viterbi compare-select operation for two-bit traceback coding
US5987490A (en) * 1997-11-14 1999-11-16 Lucent Technologies Inc. Mac processor with efficient Viterbi ACS operation and automatic traceback store
US6029267A (en) * 1997-11-25 2000-02-22 Lucent Technologies Inc. Single-cycle, soft decision, compare-select operation using dual-add processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4578800A (en) * 1982-07-12 1986-03-25 Yutaka Yasuda Synchronization circuit for a Viterbi decoder
WO1995009391A1 (en) * 1993-09-27 1995-04-06 Ntt Mobile Communications Network Inc. Minimum value/maximum value retrieving apparatus
US5726923A (en) * 1993-09-27 1998-03-10 Ntt Mobile Communications Network Inc. Minimum/maximum data detector
JPH0951278A (en) * 1995-08-08 1997-02-18 Toshiba Corp Viterbi decoder

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 06 30 June 1997 (1997-06-30) *

Also Published As

Publication number Publication date
US6272188B1 (en) 2001-08-07
EP0918292A2 (en) 1999-05-26

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