JPH0361375B2 - - Google Patents

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (i) In the case of path memory cell system (ii) In the case of random access memory (iii) In the case of path trace system Embodiment Correspondence between the embodiment and FIG. 1 Structure of the embodiment (i) Overall structure (ii) Structure of the path trace control unit Operation of the embodiment (i ) Write mode (ii) Trace mode (iii) Path trace Examples of decoding results in the embodiment Effects of the invention [Summary] In the Viterbi decoder, the contents of the path select on the side determined as a surviving path by the ACS section are After writing to memory, reading it from the newest to the oldest side and performing path tracing to find the maximum likelihood path reduces the number of memory accesses in one decoding cycle, increasing speed. At the same time, a normal random access memory can be used for the memory as well.

[Industrial application field]

The present invention relates to a Viterbi decoder, and particularly to a Viterbi decoder to which a path tracing method is applied.

The Viterbi decoder is used for maximum likelihood decoding of convolutional codes, and selects the path with the closest code distance to the received code sequence as the maximum likelihood path from among multiple known code sequences. death,
Decoded data is obtained corresponding to this selected path. This Viterbi decoder has a high error correction ability and is therefore used as a decoder for satellite communications and the like.

[Conventional technology]

(i) Path memory cell method A conventional Viterbi decoder that has been widely used is the one shown in FIG. Here, the Viterbi decoder includes a branch metric calculation section as a code distributor, an operation section consisting of a plurality of ACS circuits, a path memory, and a majority circuit that takes a majority vote based on the output of the path memory and obtains a decoded output. (maximum likelihood judgment circuit).

This branch metric calculating section calculates a branch metric from the received code of the demodulated output of the receiving device, and the branch metric is applied to the ACS circuit and added to the path metric of one symbol before. The addition result becomes a new path metric, and by comparing these path metrics, the smaller path metric is determined to be the path metric of the most likely path, and the path metric and path select signal are output.

As shown in FIG. 8, the ACS circuit is composed of an adder, a comparator, and a selector.

The path memory has a structure in which path memory cells each consisting of a selector and a flip-flop as shown in FIG. 9 are connected in multiple stages as shown in FIG. A path select signal from the ACS circuit is added to this to store the history of the most likely path. In other words, in each decoding cycle, the contents of the path memory cell on the side determined to be the surviving path by the ACS section are transferred using the path select signal.

In this Viterbi decoder, the error correction ability increases as the code constraint length increases, but since the circuit size increases exponentially, a constraint length of about 3 to 7 is adopted. .

For example, in the case of a constraint length of 7, 64 ACSs are required, which increases the circuit scale.

(ii) In case of random access memory FIG. 11 shows a conventional path memory configured using two random access memories (RAM).

Such a path memory is configured to perform multiplexed operation using two random access memories. For example, in the node number I corresponding to the path memory cell with the above-mentioned path memory, the address of one random access memory is the remaining one of 〓I/2'' and 2 ^K-1 + 〓I/2''. The selected node number is set. Then, I is set to the address of the other random access memory. In this state, data (bus information) is transferred from the data output terminal DO of one random access memory to the data input terminal DOI of the other random access memory. This is performed for all nodes, and a decoded output is obtained from an output processing section consisting of a majority circuit or the like. In the next decoding cycle, one random access memory's data input terminal DOI is transferred from the data output terminal DO of the other random access memory to the data input terminal DOI of one random access memory.
Transfer data (bus information) to. Note that 〓I/2'' mentioned above is a Gauss symbol indicating the largest integer not exceeding 1/2.

(iii) Path tracing method A path tracing method has also been proposed in which the most likely path is determined by tracing path selection information stored in a path memory. This path tracing method uses the node number and the contents of the path memory corresponding to that node number to find the node number of the node selected as the survivor, and repeats this process until the end of the path memory is reached. This method obtains the decoded output from the node number.

[Problem that the invention seeks to solve]

By the way, all of the above-mentioned conventional methods have been pointed out to have drawbacks.

In the conventional example of "(i) Path memory cell method" described in connection with FIG. 10, the path memory cell has a configuration consisting of a selector and a flip-flop, so it cannot be integrated into an integrated circuit like a random access memory. There was a problem in that it was extremely difficult to miniaturize the device configuration as a Viterbi decoder.

Further, as shown in FIG. 11, by using a random access memory as in "(ii) Case of random access memory", it is possible to configure a path memory as an integrated circuit. However, due to the multiplexing operation, when configuring a decoder with a constraint length of 7, for example, it is necessary to access two memories 64 times per one decoding cycle. Therefore, it has been extremely difficult to improve the decoding processing speed. Furthermore, in order to improve the decoding processing speed, it is possible to reduce the number of accesses by lowering the degree of multiplicity, but in this case, there is a problem that the number of memories increases.

Furthermore, the conventional path tracing method described above in "(iii) Path tracing method" traces the maximum likelihood path by repeating node number calculations according to the number of stages of the path memory. , the number of accesses to the path memory increases. This has caused a problem in that it is difficult to improve the decoding processing speed.

The present invention was created in view of these points, and aims to provide a Viterbi decoder that solves the conventionally contradictory problems of improving decoding processing speed and reducing the size of the device configuration. There is.

[Means for solving problems]

FIG. 1 is a basic block diagram of the Viterbi decoder of the present invention.

In the figure, code distribution means 115 calculates branch metrics 113 based on received codes 111.

The ACS circuit 121 adds the branch metric 113 calculated by the code distributing means 115 and the path metric one symbol before, and compares the path metric 117 of the addition output with the path metric to determine the maximum likelihood path selected. Path selection information 119 representing the path selection information 119 is output.

The writing means 125 writes the path selection information 119 into the path memory 123 according to a predetermined first period.

The trace position defining means 127 includes the path memory 1
The trace position for performing path tracing is defined based on the path selection information 119 written in 23.

The position information output means 131 outputs trace position information 129 in a repeating cycle according to the trace position.

The trace start node determining means 135 determines the trace start node 133 of the path trace based on the path metric 117.

The node definition means 137 defines a corresponding node for performing the path tracing according to the trace start node 133 and the trace position information 129.

The path tracing means 141 uses the path memory 123
Based on the path selection information 119 stored in
According to the second period, a node selected as a survivor from the defined nodes is written into the trace memory 139 as a trace result.

The decoding means 143 outputs the trace result written in the trace memory 139 in the third period of the second period as a decoded output.

Therefore, as a whole, the path selection information 119
, and obtaining the trace result and decoded output are repeatedly performed.

[Effect]

The path selection information 119 on the side determined as a surviving path by the ACS circuit 121 is stored in the path memory 1.
23, it is written into the path memory 123 during a predetermined period.

The path tracing means 141 performs path tracing by reading out data in order from newest to oldest during another predetermined period to find the maximum likelihood path. Get the decoded output from that node.

In the present invention, since the number of memory accesses in one decoding cycle is reduced, the operation becomes faster and a normal random access memory can be used as the memory.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIGS. 2 and 3 show the configuration of a Viterbi decoder in one embodiment of the present invention.

Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The received code 111 corresponds to the received code signal 211.

Branch metric 113 corresponds to branch metric signal 213.

Code distribution means 115 corresponds to distributor 215.

Path metric 117 corresponds to path metric signal 217.

Path selection information 119 corresponds to path selection signal 219.

ACS circuit 121 corresponds to ACS circuit 221.

Path memory 123 corresponds to path memory 223.

The writing means 125 corresponds to the input buffer 291 of the buffer section 263.

The trace position defining means 127 corresponds to the trace counter 227.

The trace start node 133 corresponds to the node number signal 233 of the minimum path metric.

The trace start node determining means 135 corresponds to the minimum path metric detection section 234 and the node number calculation section 236.

The node definition means 137 includes the shift register 2
It corresponds to 37.

Trace memory 139 is trace memory 2
It corresponds to 39.

The path tracing means 141 includes a selector 241
corresponds to

The decoding means 143 corresponds to the output buffer 294 of the buffer section 267.

Configuration of Embodiment Embodiments of the present invention will be described below, assuming that the above-mentioned correspondence exists.

(i) Overall configuration In FIG. 2, a branchmetric signal 213 representing a branchmetric calculated based on a received code signal 211 is sent to
15 to the ACS circuit 221. In this ACS circuit 221, the branch metric obtained by the calculation by the distributor 215 and the path metric one symbol before are added together, and the added output path metric signal 217 is supplied to the minimum path metric detection section 234. Furthermore, a path select signal 219 representing the most likely path selected by comparing the path metrics is supplied to the path trace control section 250. Based on the minimum path metric found by the minimum path metric detection unit 234,
The node number calculation unit 236 provides the path trace control unit 250 with a node number signal 233 representing the node with the minimum path metric.

A path memory length signal 251, a clock signal 253, and a mode switching signal 255 are applied to the path trace control section 250, and based on these information, the path memory
A path select signal 219 is stored in 23 and the result of path tracing is written into a trace memory 239 to obtain a decoded output signal 257.

(ii) Configuration of Path Trace Control Unit FIG. 3 shows details of the path trace control unit 250, path memory 223, and trace memory 239 shown in FIG. 2.

The path memory length signal 2 is input to the input terminal IN of the trace counter 227 and I/O counter 228 included in the path trace control unit 250.
51 is supplied, and the node number signal 233 of the minimum path metric is supplied to the input terminal IN of the shift register 237. The ripple carry output signal of the trace counter 227 is supplied to the load terminal LD of the trace counter 227 and shift register 237.

The clock signal 253 is applied to the clock input terminals of the trace counter 227, shift register 237, and I/O counter 228.
Commonly supplied to CLK. I/O
The ripple carry output signal of counter 228 is provided to its load terminal LD.

The mode switching signal 255 is sent to the inverter 261
The logic inverted signal is commonly supplied to the enable terminal EN of the trace counter 227 and shift register 237, respectively. In addition, the mode switching signal 255 is directly applied to the enable terminal EN of the I/O counter 228.
and signal selection switching terminal of selector 275
Commonly supplied to each SEL. Furthermore, the mode switching signal 255 is supplied to a buffer section 263 and also to a flip-flop 265. The output signal of flip-flop 265 is applied to buffer section 267.

The path select signal 219 is sent to the buffer section 26
3, and the decoded output signal 257 is obtained from the buffer section 267.

Trace counter 227 output terminal OUT
The trace address signal 271 obtained from the output terminal OUT of the I/O counter 228
The I/O address signal 273 obtained from
They are supplied to input terminals I ₁ and I ₂ of selector 275, respectively. Address signal 277 obtained from the output terminal OUT of this selector 275
is supplied to path memory 223 and applied to flip-flop 279. The output signal of flip-flop 279 is supplied to trace memory 239.

6-bit selection control signal 281 obtained from the output terminal OUT of the shift register 237
is the selection control signal terminal SC of the selector 241
The 64-bit read path select signal 283 from the buffer section 263 is supplied to the input terminal.
It is now applied to IN. A 1-bit output signal from the output terminal OUT of selector 241 is supplied to shift register 237 and flip-flop 285. The output signal of flip-flop 285 is supplied to buffer section 267.

Operation of the Embodiment FIG. 4 shows the operation timing of the Viterbi decoder according to the embodiment of the present invention. Here, diagram a is
A clock signal 253 is shown. b shows the repetition of the soft decision data D in the decoding cycle in the Viterbi decoder according to the embodiment of the present invention. Note that this soft decision data D is external data to the path trace control unit 250.

Also, c indicates the path select signal 219, but as path select information PD,
The timing at which the data is written to the path memory 223 is shown. d indicates the timing of writing the trace result in the trace memory 239.

Furthermore, e indicates a mode switching signal 255 that determines the operation mode of the path trace control section 250.

However, here, the explanation will focus on the period before and after the decoding cycle in which soft decision data Dn is taken as external data.

Hereinafter, reference will be made to FIGS. 2 to 4.

When the mode switching signal 255 takes a "low" level (a mode in which path selection information is not written), an inverted signal from the inverter 261 causes the
Trace counter 227 and shift register 237 are activated. In this state, at the first clock, the node number signal 233 of the minimum path metric calculated based on the received code signal 211 is placed in the shift register 237.
Further, a path memory length signal 251 specifying the physical length of the path memory 223 is transmitted to the trace counter 22.
7 and the I/O counter 228.

In such a state, the trace counter 227 and the I/O counter 228 perform counting in response to the clock signal 253, and the shift register 2
37 is for shifting the number state.

(i) Write Mode Now, when the mode switching signal 255 assumes a "high" level and enters the "path select signal write mode", the I/O counter 228 and the input buffer 291 of the buffer section 263 are activated. Furthermore, since the mode switching signal 255 is supplied to the signal selection switching terminal SEL of the selector 275, in the "path select signal write mode", the input terminal _I2 side is selected, and the I/O counter 228 O address signal 273 is selected and output as address signal 277. Also, by this mode switching signal 255, the buffer section 236
input buffer 291 is activated. Therefore, information of path selection information PD _(o-1) is written into path memory 223 according to the address represented by address signal 277.

(ii) Trace mode After the above-mentioned “path select signal write mode” operation, the clock signal 255
At a time delayed by one clock, the mode switching signal 255 takes a "low" level. In response, trace counter 227 is activated to count clock signal 253. In addition, the selector 275 responds to the mode switching signal 255.
The input terminal _I1 side of is selected, and its trace address signal 271 becomes an address signal 277 and is supplied to the path memory 223, and becomes an address for reading data. In this case, the buffer section 263
Since the output buffer 292 of is activated, the read path select signal 283 read from the path memory 223 is supplied to the selector 241.

Further, the shift register 237 activated in response to the mode switching signal 255 performs a shift operation in response to the clock, and the selection control signal 281, which is an output signal, is sent to the selector 241.
to select the node that should be the most likely path. The 1-bit signal representing the node thus selected is sent to the flip-flop 2.
85 and then supplied to the buffer section 267 with a one clock delay. In the trace mode, the input buffer 2 of the buffer section 267
93 is activated, the selected node is written to trace memory 239.

(iii) Path tracing By the way, path tracing performed in the circuit operation as described above will be explained using FIG. 5.

Clock signal 253 in the form shown.
Path selection information PD is written into the path memory 223 in accordance with the path selection information PD. Initially, the path metric values for each node are [82, 82, 82, 82,
64, 78, 76, 62], the minimum path metric value is (62), so that node 7 is placed in the shift register 237. Path tracing is performed from this state.

The node calculation in that case is shown. First, in the first decoding cycle, the node (N _i ) with the minimum path metric and the path memory content (P _i ) indicated by that node (N _i ) are stored in the path memory 2.
23. Accordingly, the next node (N _{i +1} ) according to the trace is N _{i +1} = 2 ^K-2 × P _i + "N _i /2".

This node (N _i+1 ) is selected by the selector 241. This kind of behavior
Path tracing is performed repeatedly every clock, and the trace results T _(o-1) are sequentially circulated and stored in the trace memory 239. Then, in the next "path select signal write mode", the output buffer 294 of the input buffer 293 is activated and output as the decoded output signal 257.

The above operations are repeated to perform decoding. That is, when the counting state of the trace counter 227 in response to the clock signal 253 reaches the path memory length, a ripple carry output signal is generated. In response, the states of trace counter 227 and shift register 237 return to their original states, and the above-described operation is repeated from the beginning. The same applies to the I/O counter 228. In this way, within the path memory length, the I/O counter 228
Path tracing is performed according to the path selection information PD written according to the counting status of
The decoding operation is repeated.

Example of Decoding Results in Embodiment FIG. 6 shows error rate characteristics in a Viterbi decoder according to an embodiment of the present invention. Here, the horizontal axis shows the number of traces, and the vertical axis shows the bit error rate BER.

A curve 551 is the bit error rate characteristic obtained when Es/No (signal-to-noise ratio) is -0.5 dB. In addition, curve 553 shows that Es/No is +
This is the characteristic of the bit error rate obtained in the case of 0.5 dB. However, Es/No of straight line 561 is -0.5dB
In the case of , the straight line 563 is the respective theoretical bit error rate when Es/No is +0.5 dB.

As can be seen from this result, if the number of traces is 2 or more, the bit error rate will be lower than its theoretical value. Furthermore, increasing the number of traces has little effect on the bit error rate results.

〔Effect of the invention〕

As described above, according to the present invention, after the path selection information of the side determined as a surviving path is written into the path memory, it is sequentially read out from the newest one, and the most likely path is determined by performing path tracing. By configuring this, memory access becomes faster and a normal random access memory can be used as the memory, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of a Viterbi decoder according to the present invention, FIG. 2 is a block diagram of the structure of a Viterbi decoder according to an embodiment of the present invention, and FIG. 3 is a part of the embodiment of the present invention shown in FIG. Block diagram showing details, No. 4
The figures are timing diagrams showing the operation in the embodiment of the present invention shown in Figs. 2 and 3, Fig. 5 is an explanatory diagram of path trace, and Fig. 6 is a diagram showing the bit error rate in the Viterbi decoder according to the embodiment of the present invention. A characteristic diagram, FIG. 7 is an explanatory diagram of a conventional Viterbi decoder, and FIG. 8 is a detailed block diagram explaining the configuration of the ACS circuit shown in FIG. 7.
FIG. 9 is an explanatory diagram of the configuration of a conventional path memory cell, FIG. 10 is an explanatory diagram of a conventional path memory, and FIG. 11 is an explanatory diagram showing the configuration of another conventional path memory. In the figure, 111 is a received code, 113 is a branch metric, 115 is a code distribution means, and 117
is path metrics, 119 is path selection information,
121 is an ACS circuit, 123 is a path memory, 12
5 is a writing means, 127 is a trace position defining means,
129 is trace position information, 131 is a position information output means, 133 is a trace start node, 135 is a trace start node determination means, 137 is a node definition means, 139 is a trace memory, 141 is a path trace means, 143 is a decoding means, 211 is a received code signal, 213 is a branch metric signal, 2
15 is a distributor, 217 is a path metric signal, 2
19 is a path select signal, 221 is an ACS circuit,
223 is a path memory, 227 is a trace counter, 237 is a shift register, 239 is a trace memory, 241 is a selector, 251 is a path memory length signal, 253 is a clock signal, 255 is a mode switching signal, 257 is a decoding output signal, 275 is a A selector 277 is an address signal.

Claims (1)

[Claims] 1. A code distributing means 115 that calculates a branch metric 113 based on the received code 111, and a code distributing means 115 that adds the branch metric 113 calculated by the code distributing means 115 and the path metric one symbol before. , the path metric 117 of the addition output, and path selection information 11 representing the maximum likelihood path selected by comparing the path metric.
ACS circuit 121 that outputs 9, and writing means 125 that writes path selection information 119 to path memory 123 according to a predetermined first period.
and trace position defining means 1 for defining a trace position for performing path tracing based on the path selection information 119 written in the path memory 123.
27; position information output means 131 for outputting trace position information 129 in a repeat cycle according to the trace position; trace start node determining means 135 for determining a trace start node 133 of the path trace based on the path metric 117; a node definition means 13 for defining a corresponding node for performing the path tracing according to the trace start node 133 and the trace position information 129;
7, and according to the second period based on the path selection information 119 stored in the path memory 123, the node selected as a survivor from the defined nodes is stored as a trace result in the trace memory 13.
9; and a decoding means 143 for outputting the trace result written to the trace memory 139 as a decoded output in a third period of the second period. A Viterbi decoder, characterized in that the Viterbi decoder is configured to repeatedly obtain the trace result and the decoded output.