JPH04283842A - Tracing control system - Google Patents

Abstract

PURPOSE:To freely trace a large range by setting a necessary tracing interval value in an interval register. CONSTITUTION:A number register 14 counts up and is updated at a specific period and a number register decoding circuit 12 decodes the data in the number register 14 and outputs an internal write enable signal when the data in the interval register 11 coincides with the data of the interval counter 13. A trace data holding circuit 16 holds trace data with the internal write enable signal, the interval register 11 holds the trace interval, and the interval counter 13 is updated every time a trace indication is made. Therefore, only when the values of the interval register 11 and interval counter 13 match each other, the trace data are held. Thus, a constant amount of trace data can be held at free intervals, so the data are rather rough, but the large range can be traced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace control method in an information processing apparatus. In information processing equipment,
It is necessary to collect trace information of various data inside the device. Therefore, there is a need for a trace control method that performs efficient tracing with a small amount of hardware.

0002

2. Description of the Related Art As a conventional trace control method, there is one shown in FIG. 4, for example. In Figure 4, first,
Initial data is set in number register 1. An external write enable signal supplied from the outside and data of number register 1 are input to number register decoding circuit 2, and number register decoding circuit 2 generates internal write enable signals 0 to 3 based on the input data.

[0003] The number register 1 is incremented by +1 by the number register update circuit 3 every time the external write enable signal is turned on. The trace data holding circuit 4 holds input trace data using an internal write enable signal. The held trace data is selected by the output trace data selection circuit 5 based on the output selection signal generated by the number register decoding circuit 2, and is output to the outside.

FIG. 5 shows this conventional time chart. In FIG. 5, number register 1 is 0, 1, 2, 3.
When the count is 0, the internal write enable signal 0 is on, and when it is 1, the internal write enable signal 1 is on, and the count is 2.
, 3, internal write enable signals 2 and 3 are turned on.

[0005] Data A,
B, C, and D are held, and when number register 1 counts up in the next cycle, data E, F, G, and H are held in holding circuits 4-0, 4-1, 4-2, and 4-3. .

[0006]

[Problems to be Solved by the Invention] However, in such a conventional trace control method, trace data is traced every cycle in synchronization with an external write enable signal and a clock signal supplied to the trace circuit. In addition, the trace data holding circuit generally requires a considerable amount of hardware (FF, memory, etc.), and the amount of trace data that can be traced at one time depends on the amount of hardware. If you want to trace a not-too-large range in detail, there is no problem, but it may be rough to some extent, but instead, when tracing a large range freely, it is necessary to retain the necessary trace data. The problem was that it was not possible.

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a trace control method that can freely trace a large range.

[0008]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, numeral 14 is a number register that counts up and is updated at a predetermined period;
16 is a number register decoding circuit that decodes the data in the number register 14 and outputs an internal write enable signal when the data in the interval register 11 and the data in the interval counter 13 match; 16 is a number register decoding circuit that decodes the data in the number register 14 and outputs an internal write enable signal; A trace data holding circuit 11 holds a trace interval, an interval register 13 holds a trace interval, and an interval counter 13 is updated every time a trace instruction is issued.

[0009]

[Operation] In the present invention, the data in the number register is decoded and an internal write enable signal is generated only when the value of the interval register that holds the trace interval matches the value of the interval counter that is updated every time a trace instruction is issued. , the input trace data is held in the trace data holding circuit by the generated internal write enable signal.

[0010] In this way, since a certain amount of trace data can be held at free intervals, it is possible to trace a large range, although it is rough to some extent.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. 2 and 3 are diagrams showing an embodiment of the present invention. In FIG. 2, 11 is an interval register, and a trace interval value is set in the interval register 11. Trace spacing values are selected as needed.

The output value (trace interval value) of the interval register 11 is output to a number register decode circuit 12 and an interval counter 13, respectively. The interval counter 13 is incremented by +1 every time the external write enable signal is turned on. However, the data of the interval counter 13 before updating is
When the data matches the interval register 11,
Instead of being added +1, it is set to 0.

The count value of the interval counter 13 is output to the number register decoding circuit 12. 14
is a number register, and number register 14 is
The external write enable signal turns on, and the data in interval register 11 and interval counter 1
When the data of 3 match, the number register update circuit 15 counts up by +1, and also sets 0 at a predetermined period.

The data of the number register 14 is outputted to the number register decoding circuit 12, and a number register update signal is inputted to the number register 14 from the number register decoding circuit 12. The number register decoding circuit 12 decodes the data of the number register 14 only when the data of the interval register 11 and the data of the interval counter 13 match, and generates internal write enable signals 0 to 3 based on the external write enable signal. , trace data holding circuit 1
Output to 6.

The trace data holding circuit 16 is composed of a plurality of holding circuits 16-0, 16-1, 16-2, and 16-3, and holds input trace data using internal write enable signals 0 to 3. The trace data held in the trace data holding circuit 16 is selected by the output trace data selection circuit 17 by the data in the number register 14 being decoded by the number register decoding circuit 12 and generated output selection signals 0 to 3. Output to the outside.

Next, a time chart of this embodiment is shown in FIG. In FIG. 3, interval register 1 is shown here.
The trace interval value 2 is set to 4. The interval counter 13 counts up 0, 1, and 2 each time the external write enable signal is turned on, and is set to 0 when the count value 2 and the trace interval value 2 of the interval register 11 match.

The number register 14 starts counting when the external write enable signal is turned on, and when the output value 2 of the interval register 11 and the count value 2 of the interval counter 13 match, the number register 14 counts 0, 1, 2, 3. and is set to 0 in the next cycle. Output value 2 of interval register 11 and interval counter 1
When count value 2 of 3 matches, number register 1
The output values 0, 1, 2, and 3 of 4 are decoded, and internal write enable signals 0 to 3 are turned on.

Data C, F, I, and L are held in holding circuits 16-0, 16-1, 16-2, and 16-3 by internal write enable signals 0 to 3, respectively. In this way, since the trace interval is set as necessary, a large range can be freely traced and necessary trace data can be retained.

[0019]

[Effects of the Invention] As explained above, the necessary trace interval value is set in the interval register, and when the data in the interval register and the data in the interval counter match, the data in the number register is decoded and the input trace data is Because we decided to keep
You can freely trace a large range, and you can freely trace the trace data you need.

[Brief explanation of the drawing]

[Fig. 1] Diagram explaining the principle of the present invention

[Fig. 2] A diagram showing an embodiment of the present invention.

[Figure 3] Time chart explaining operation

[Figure 4] Diagram showing a conventional example

[Figure 5] Conventional time chart

[Explanation of symbols]

11: Interval register 12: Number register decoding circuit 13: Interval counter 14: Number register 15: Number register update circuit 16: Trace data holding circuit 16-0 to 16-3: Holding circuit 17: Output trace data selection circuit

Claims (1)

[Claims] 1. A number register (14) that counts up and is updated at a predetermined period, and a number register decode circuit (14) that decodes data in the number register (14) and outputs an internal write enable signal.
12), and a trace data holding circuit (16) that holds input trace data by the internal write enable signal.
), the information processing device includes an interval register (11) that holds a trace interval, and an interval counter (13) that is updated every time a trace instruction is issued, and the interval register (11) and the interval counter (13) A trace control method characterized by retaining input trace data only when the values of match.