JP3202326B2 - Hierarchical synchronization controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous control system for operating a plurality of processors in parallel. In a parallel processing device, all processors end a certain process,
When a certain state is reached, it is necessary to notify the timing to all processors and synchronize them.

Further, if a parallel processing device can have a flexible configuration that can synchronize not only all processors but also some processors, very complicated processing can be performed by distributed processing. However, it can be executed efficiently.

[0003]

2. Description of the Related Art Conventionally, as shown in FIG. 8 or 9, synchronization is achieved by returning operation results such as logical product and logical sum of synchronization signals output from all processors to all processors. FIG. 8 shows that when all of the n synchronization signals output from the n processors 80 to 82 become significant signals, the logical product circuit 83 outputs the n processors 80 to 82.
, A synchronization signal notifying the timing is returned.

FIG. 9 shows that the current flows through the resistor 93 when the internal state of any one of the processors becomes a significant state. Processors 90-92 are all equal "
An L-level synchronization signal is received. Normally, the n processors 90 to 92 receive the "H" signal.

[0005]

In the above-mentioned conventional system, although synchronization can be achieved as a whole, it is difficult to achieve synchronization only in some processors. Even if only some processors can be synchronized in hardware, it is still difficult to change the combination at the time of execution, and there is a problem of lack of flexibility. Naturally, it is not possible to use one system for multiple users.

The present invention has been made in view of such conventional problems, and is intended to divide a plurality of processors included in a parallel processing system into various combinations and flexibly change the configuration. It is an object of the present invention to provide a device for synchronous control necessary for a computer.

[0007]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims.

That is, the invention of claim 1 has at least two processors, one of which is based on a synchronization signal output from another processor, and the other processor is one of the processors. Based on the synchronization signal to be output, or based on a combination of these synchronization signals, in a parallel processing system configured to proceed with processing , at least one of the synchronization signals among the synchronization signals is input, and each input signal is input. means for performing a predetermined operation for the synchronizing signal, the operation result has a synchronous basic circuit having means for outputting as at least one of the synchronizing signals, lower synchronous basic circuit was placed in the upper
The synchronization signal output by the synchronization basic circuit
One or more processors that perform processing output each
Synchronization signal or one or more synchronization bases placed below
While inputting the synchronization signal which each circuit outputs,
With respect to the higher-level synchronous basic circuit, and
One or more processors, or the one or more synchronous basic circuits
The synchronization signal is output to the
Output one or more synchronization basic circuits.
Sync signal and higher-level sync basic circuit output
Input a synchronization signal to be output or a synchronization signal output by itself.
And for one or more of the synchronization basic circuits, and
Synchronous basic circuit placed higher than the above, or to itself
Output multiple synchronization signals in a hierarchical configuration
A hierarchical synchronization control device comprising a basic circuit .

[0009]

According to a second aspect of the present invention, there are provided means for performing k predetermined operations on n input signals and outputting k operation results, and selecting one of the k operation results. And a means for selecting the operation result of (i) and outputting n synchronization signals.

According to a third aspect of the present invention, in addition to the input of n synchronization signals composed of m lines, k types of predetermined operations are performed on the n input signals, and k types of operation results are obtained. M types of calculation means to be output, and m types of selection means to select one calculation result from among k types of calculation results output by one type of calculation means and to output n synchronization signals. This is a hierarchical synchronization control device provided with a basic synchronization circuit.

Further, the invention according to claim 4 is characterized in that the multiplexed n
Means for inputting the number of synchronization signals, decoding each input signal, and outputting as n synchronization signals composed of m pieces, and n elements composed of m pieces output from the m kinds of selection means.
Means for encoding a plurality of synchronization signals and outputting the multiplexed n synchronization signals as a synchronization basic circuit.

According to a fifth aspect of the present invention, there is provided a basic circuit for inputting n synchronization signals composed of m lines output by the m kinds of selection means and outputting n synchronization signals composed of m lines. A second operation means for inputting m signals and outputting j operation results, and selecting one operation result from the j operation results and outputting m signals This is a hierarchical synchronization control device provided with a second basic circuit having n types of circuits constituted by the second selection means.

Further, the invention according to claim 6 is characterized in that the multiplexed n
Means for inputting the number of synchronization signals, decoding each input signal, and outputting as n synchronization signals composed of m lines, and n synchronization signals composed of m lines outputted by the second basic circuit. It encodes the signal, a hierarchical synchronization control and means for outputting as the n synchronization signals are multiplexed.

[0015]

According to the present invention, a circuit in which an arithmetic unit, a selector, and the like are combined has a basic structure, and the circuits are hierarchically connected to enable flexible synchronization. The use of the selector and the hierarchical configuration make it easy to synchronize only some processors.

Further, by making the control of the selector programmable, the combination of processors to be synchronized can be freely changed. Furthermore, the hierarchical configuration allows one signal to be treated as a different signal by the processor, so that one system can be used by a plurality of users.

[0017]

FIG. 1 shows an example of a basic hierarchical structure of the present invention. In this embodiment, “n + 1” inputs and “n”
The synchronous basic circuits 8 to 10 having +1 "outputs are connected to n
Connections are made hierarchically at a time. Each synchronous basic circuit 8 ~
Processors 1 to 7, input to 10 "1 to n",
Or connect the output of the lower level basic synchronization circuit,
The output of the upper level synchronous basic circuit is connected to the (n + 1) th input.

With respect to the output side of the synchronous basic circuits 8 to 10, the selectors 14 to 16 included therein are used to output "1 to 1".
Outputs up to n "are returned to the inputs of the processors 1 to 7 or the lower level synchronous basic circuit, and the" n + 1 "th output is provided as an input of the upper level synchronous basic circuit.

It should be noted that the number of synchronization signals received from the upper-level synchronization basic circuit and the number of signals output to the upper-level synchronization basic circuit are not necessarily limited to one. It should just be given by.

When synchronizing as a whole, an arithmetic unit 11, which takes a logical product of synchronizing signals output from several processors, and the like,
12 is applied to the lowermost synchronous basic circuits 8 and 9
Take it out from the "n + 1" th output and give it to the upper synchronization basic circuit. The upper-level synchronization basic circuit receiving this takes the logical product of the synchronization signals output from the several lower-level synchronization basic circuits, and outputs this to the higher-level synchronization basic circuit.

In this manner, the uppermost synchronous basic circuit 10
(For example, the logical product of the output signals of all processors) is collected by the arithmetic unit 13 and then returned to its own input. The highest-order synchronization basic circuit 10 selects the synchronization signal transmitted by itself by the selector 16 and returns it to the lower-order synchronization basic circuit.

The lower synchronization basic circuit that receives this signal selects the synchronization signal returned from the uppermost synchronization basic circuit 10 again using a selector, and returns it to the lower synchronization basic circuit. In this way, finally, the synchronization signal obtained as a result of performing the operation in the entire synchronization basic circuit is returned to all processors.

On the other hand, when partially synchronizing, signals collected in the synchronization basic circuit are not output to the upper synchronization basic circuit, and the result of the operation is returned to the lower synchronization basic circuit or the processor. May be set to a selector.

Next, a description will be given of an embodiment of a synchronous basic circuit capable of performing synchronous control by adopting a hierarchical structure as described above. FIG. 2 shows the first embodiment. This synchronous basic circuit is a 1-bit register 2
4 and by setting its value appropriately,
Either the output of the AND circuit 21 or the output of the OR circuit 22 can be selected by the selector 23.

In the first embodiment, since all processors are given the same value, it is difficult to synchronize only some of the processors, as in the prior art. However, it is possible to make settings such as taking the logical product of the result of the logical sum.

FIG. 3 shows a second embodiment. This synchronous basic circuit performs a logical operation such as a total logical product, a logical sum of two inputs, a logical product of three inputs, and the like on inputs from "1" to "n" to obtain k outputs. And a logical operation unit 31 that can perform the operation. The selectors 32 to 35 extract and output one of the k types of operation results according to the value of the memory 36.

The logical operation unit 31 and the selectors 32 to 3
The same result can be obtained even if the order of 5 is reversed from the illustrated example. The same applies to a combination of a mask operation and an arithmetic unit. In this embodiment, the operation of the selectors 32-35 is controlled by the memory 36.

However, the control means is not limited to a memory, but may be any means such as a register that can hold a value.
In addition, the flexibility is poor, but it may be fixed in hardware without using a memory or the like.

FIG. 4 shows a third embodiment. In the third embodiment, each input of the synchronous basic circuit is constituted by an m-bit signal line. In this case, each bit from each input
A, it is possible to obtain a "n + 1" the input.

As in the case shown in the second embodiment,
By combining the logical operation unit 41 and the selectors 42 to 45 controlled by the memory 46, “n + 1” outputs can be obtained from “n + 1” inputs. In the third embodiment, from such “n + 1” inputs, “
It is possible to obtain n + 1 "outputs corresponding to m-bit signal lines.
As can bets, by providing the m pieces of unit circuits 47 to 49, which is constituted by a signal line of m bits "n +
1 "output is obtained.

FIG. 5 shows a fourth embodiment. In this basic synchronization circuit, the decoders 510 to 513 decode "n + 1" input signals in which m-bit signals are multiplexed, and output "n + 1" inputs composed of m-bit signal lines. create. This input is processed by m types of unit circuits 507 to 509 having a logical operation unit 501 and selectors 502 to 505 controlled by a memory 506, as in the third embodiment.

Each of the unit circuits 507 to 509 outputs
"n + 1" outputs are output to "n + 1" encoders 51.
According to 4-517, m signals are multiplexed in units and output. By doing so, more independent information than the number of input / output signal lines of the processor can be handled.

FIG. 6 shows a fifth embodiment. In this basic synchronous circuit, m types of unit circuits 607 to 609 each having a logical operation circuit 601 and selectors 602 to 605 controlled by the contents of the memory 606 are provided in the same manner as in the third embodiment shown in FIG. I have it. Thus, “n + 1” outputs composed of m-bit signal lines can be obtained from “n + 1” inputs composed of m-bit signal lines.

It is composed of the m-bit signal line obtained here.
The “n + 1” outputs have arithmetic units 614 to 617 and selectors 618 to 629 under the control of the memory 630, and obtain “n + 1” unit circuits 610 to 613 that obtain m outputs from m inputs. Processed by

As a result, more flexible synchronization control becomes possible. The order of the unit circuits 607 to 609 for performing "n + 1" input / output operations and the unit circuits 610 to 613 for performing m input / output operations is not limited to that shown in FIG. Needless to say.

FIG. 7 shows a sixth embodiment. This synchronous basic circuit is similar to the fifth embodiment shown in FIG.
m types of unit circuits 707 to 709 handling n + 1 "input / output signals and" n "handling m input / output signals
+1 "type unit circuits 714 to 717. The input synchronization signal is" n + 1 "signals obtained by multiplexing m-bit signals.

A unit circuit 707 for handling "n + 1" input / output signals includes a logical operation unit 701 and a memory 706.
Selectors 702 to 705 that are controlled by a unit circuit 71 that handles m input / output signals.
Similarly, 4 to 717 have arithmetic units 718 to 721 and selectors 722 to 733 controlled by the memory 734.

Therefore, in the sixth embodiment, similarly to the fourth embodiment, each input is decoded by the decoders 710 to 713 to extract "n + 1" synchronization signals composed of m bits. ing. Further, encoders 735 to 738 are provided at the output stage, and m-bit signals are multiplexed by the encoders to finally generate "n + 1" output signals. Therefore, it is possible to handle more independent information than m bits.

[0039]

As described above, according to the present invention,
Flexible synchronization processing including partial synchronization of an arbitrary number of processors becomes possible. Therefore, the parallel processing system can appropriately change the configuration of the processor so as to be optimal for each process, and thus can easily deal with complicated and various processes.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a hierarchical configuration.

FIG. 2 is a diagram showing a first embodiment of a synchronous basic circuit.

FIG. 3 is a diagram showing a second embodiment of the synchronous basic circuit.

FIG. 4 is a diagram showing a third embodiment of the synchronous basic circuit.

FIG. 5 is a diagram showing a fourth embodiment of the basic synchronization circuit.

FIG. 6 is a diagram showing a fifth embodiment of the synchronous basic circuit.

FIG. 7 is a diagram showing a sixth embodiment of the synchronous basic circuit.

FIG. 8 is a diagram showing a conventional technique.

FIG. 9 is a diagram showing a conventional technique.

[Explanation of symbols]

1 to 7, 80 to 82, 90 to 92 Processor 8 to 10 Basic synchronization circuit 11 to 13, 614 to 617, 718 to 721 Operation unit 14 to 16, 23, 32 to 35, 42 to 45, 502
505, 602 to 605, 618 to 629, 702 to 7
05, 722-733 Selector 21, 83 AND circuit 22 OR circuit 24 Register 31, 41, 501, 601, 701 Logical operation unit 36, 46, 506, 606, 630, 706, 734
Memory 47-49,507-509,607-613,707
To 709, 714 to 717 Unit circuit 93 Resistance 510 to 513, 710 to 713 Decoder 514 to 517 Encoder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/16-15/177 G06F 9/46

Claims (6)

(57) [Claims] At least two processors are provided, one of which is based on a synchronization signal output by another processor, and the other of which is based on a synchronization signal output by the one processor. Alternatively, in a parallel processing system configured to proceed with processing based on a combination of these synchronization signals,
Of inputs the at least one synchronization signal, each
Means for performing a predetermined operation for the inputted synchronizing signals, the operation result has a synchronous basic circuit having means for outputting as at least one of the synchronizing signals, lower synchronous basic circuit, location in the upper Synchronous basic circuit
The synchronization signal to be output and the processing related to
Synchronization signals output by more than one processor, respectively, or
One or more synchronization basic circuits placed below each
Input the synchronization signal to be output and place
The synchronized basic circuit and the one or more processes
Signal or the synchronization signal to the one or more synchronization basic circuits.
Signal, and the upper synchronization basic circuit
A synchronization signal output by each of the plurality of synchronization basic circuits,
A synchronization signal output by a synchronization basic circuit placed at a higher level,
Or while inputting the synchronization signal output by itself,
For one or more synchronous basic circuits and above
Outputs a synchronization signal to the placed basic synchronization circuit or itself.
Multiple synchronous basic circuits in a hierarchical configuration
A hierarchical synchronization control device. 2. The k predetermined signals for n input signals
Means for performing the above operation and outputting k different operation results
And one of the k calculation results is selected
And a means for outputting n synchronization signals.
The hierarchical synchronization control device according to claim 1, further comprising a circuit . 3. An input of n synchronization signals composed of m lines.
And k predetermined performances for n input signals.
M types of operations that perform calculations and output k different operation results
Calculation means and k kinds of operations output by one kind of calculation means.
One operation result is selected from the operation results, and n synchronization signals are selected.
Basic circuit having m kinds of selecting means for outputting a signal
3. The hierarchical synchronization control device according to claim 2, further comprising: 4. A multiplexed n synchronization signal is input.
At the same time, each input signal is decoded and n
Means for outputting a synchronization signal of
Encoding n synchronization signals composed of m lines output by the stage
And multiplexed and output as n synchronized signals.
A hierarchical basic circuit according to claim 3, wherein a synchronous basic circuit comprising:
Synchronous control device. 5. The method according to claim 1, wherein said m kinds of selection means output m lines.
Input n synchronization signals to be composed, and n synchronization signals composed of m
Is a basic circuit that outputs a synchronization signal of
Second operation means for inputting and outputting j kinds of operation results
And select one calculation result from j calculation results
And a second selecting means for outputting m signals.
Claims: A second basic circuit comprising n types of circuits is provided.
3. The hierarchical synchronization control device according to 3. 6. A multiplexed n synchronization signal is input.
At the same time, each input signal is decoded and n
Means for outputting as a synchronization signal of the second basic circuit
Encodes n synchronization signals composed of m lines output by
Means for outputting the multiplexed n synchronization signals.
6. The hierarchical synchronization control device according to claim 5, further comprising: