JP5071707B2 - Data processing apparatus and control method thereof - Google Patents

Description

  The present invention relates to a data processing apparatus including a unit whose circuit can be reconfigured and a control method thereof.

  Patent Document 1 describes image processing of genetic programming (GP), which was devised based on a genetic algorithm (GA), which is one of the optimization methods imitating the evolution process of living organisms. Describes that the tree-structured image conversion automatic creation method applied to the above is used for a character string extraction method for printed matter.

  Further, Patent Document 1 describes the following. This technique realizes image conversion processing from an input image to an output image by combining a plurality of image conversion processing filters prepared in advance into a tree structure having an arbitrary shape. This method uses an image conversion processing filter Fn having one or more input / output means and one output means. The image to be processed is input from all leaf nodes (terminals) in the tree structure, and is subjected to different processing depending on the combination of filters. They are sequentially synthesized by image conversion processing, and finally output as one image. Depending on the combination of filters, it is possible to construct a complex image conversion process in which different processes are performed for each region and purpose, and the results are appropriately combined.

Patent Document 2 describes an integrated circuit device of a type that reconfigures various data paths by changing the connection of a plurality of types of processing elements. This integrated circuit device has a RAM element that functions as a RAM in addition to an element for arithmetic logic operation as a processing element.
JP 2004-362440 A JP 2006-285386 A

  A tree-structured image conversion program in which GAGP is applied to image processing is an application program in which a plurality of image conversion processing filters are combined in a tree structure. The integrated circuit device disclosed in Patent Document 2 is an integrated circuit device (dynamically reconfigurable LSI) that can dynamically reconfigure a circuit in several clock cycles or even one clock cycle, for example. Therefore, by forming one or a limited number of functions of a plurality of image conversion processing filters included in the image conversion program as a circuit and sequentially configuring them into dynamically reconfigurable LSIs, various tree structure shapes can be obtained. The processing by the image conversion program whose function is instructed can be executed by a circuit (hardware) developed exclusively for executing the program using less hardware resources. Therefore, the processing result can be obtained at a higher speed than when the image conversion program is run on a processor whose circuit configuration is basically unchanged.

  When the information obtained by the image conversion process is used to control a device, for example, to control an automobile safely, a high processing speed is required. Further, the image conversion program may be different depending on the environment in which the image data is obtained, the recognition object to be extracted from the image data, and the like. Therefore, there is a demand for a data processing apparatus that can process the functions of an image conversion program such as a tree structure at high speed and that can also quickly cope with the functions of image conversion programs having different structures.

One aspect of the present invention is a reconfiguration unit including a plurality of elements for configuring a circuit and an internal wiring for connecting the plurality of elements, wherein the connection of the plurality of elements by the internal wiring is changed. Thus, the data processing device includes a reconfiguration unit that can reconfigure the circuit, and a control unit that outputs reconfiguration information including connection information of a plurality of elements in order to reconfigure the circuit of the reconfiguration unit. The plurality of elements include a plurality of calculation elements for executing at least one kind of calculation and a plurality of memory elements, and changing at least one of the plurality of memory elements by changing connection of internal wiring The processing circuit including at least one of the calculation elements can be set as an input target or an output target. The data processing device further includes for each of the processing of a plurality of processes involving the input and output of data, the first memory element an input object, processing for each of the processing as an output target of the second memory element a first connection information for configuring the circuit (the first processing circuit), a second memory element an input object, the first memory element and the output target performs each processing processor (second And a connection information library in which second connection information for configuring the second processing circuit) is stored. Then, in order to execute the plurality of processes in order, the control unit selects, from the connection information library, the connection information for which the memory element that is the output target in the previous process is the input target, and the selected connection information is selected. Output reconfiguration information.

  In this data processing device, for each of a plurality of processes involving data input / output, the control unit outputs reconfiguration information including connection information prepared in the connection information library, whereby A circuit for executing the process is configured. Therefore, a plurality of processes can be executed using a circuit designed specifically for the processes, and can be executed at a high speed with fewer hardware resources. Furthermore, the circuit reconfigured in the reconfiguration unit by the reconfiguration information including the first or second connection information prepared in the connection information library inputs and outputs the memory elements in the reconfiguration unit that can be accessed by internal wiring. The target of. Therefore, the memory access time required to input / output data to / from the external memory via the input / output interface and the external bus can be omitted or shortened. For this reason, a processing speed can be improved.

  Further, the connection information library includes a first processing circuit having a first memory element as an input target and a second memory element as an output target for each of a plurality of processes involving data input / output. The first connection information and second connection information for configuring a second processing circuit having the second memory element as an input target and the first memory element as an output target are stored. Therefore, in order to execute a plurality of processes in order, the control unit selects, from the connection information library, connection information for which the memory element that is the output target in the previous process is the input target, and the selected connection information is selected. By outputting the included reconfiguration information, it is possible to flexibly select an input target memory element and an output target memory element. For this reason, even if a plurality of memory elements to be input / output are connected by a common bus, or without using a redundant circuit configuration that is selected by switching with a selector, the memory to be input / output is supplied to the reconfigurable unit. A circuit that allows flexible selection of elements can be reconfigured. That is, by reconfiguring a circuit optimized to input / output a specific input / output memory element in the reconfiguration unit, a memory element to be input / output can be flexibly selected.

  Furthermore, the connection information included in the reconfiguration information can be selected based on the order in which a plurality of processes are executed. This means that the control unit can dynamically generate reconfiguration information. That is, in this data processing apparatus, when the order in which a plurality of processes are executed is changed, it is not necessary to regenerate information for reconfiguring the reconfiguration unit from the beginning. By providing the control unit with information regarding the order in which a plurality of processes are executed, the control unit can dynamically output reconfiguration information that matches the new order. The change in the order of executing the plurality of processes may be supplied from the outside of the data processing apparatus, or may be given by a result inside the data processing apparatus, for example, an operation result of a circuit configured in the reconfiguration unit. .

  The reconfigurable unit includes an input interface and an output interface, and by changing the connection of internal wiring, the input interface is set as an input target of a processing circuit including any of a plurality of arithmetic elements, and the output interface is set in the processing circuit. It is desirable that it can be output. Further, the connection information library includes a third processing circuit for configuring a third processing circuit having the input interface as an input target and the first memory element or the second memory element as an output target for each of the plurality of processes. The connection information and the fourth connection information for configuring the fourth processing circuit having the first memory element or the second memory element as an input target and the output interface as an output target are stored. desirable.

  The fourth connection information can be merged with the first connection information, the second connection information, and the third connection information. That is, in the connection information library, the first connection information has an output interface as an output target in addition to the second memory element, and the second connection information has an output interface as an output target in addition to the first memory element. The connection information 3 includes the output interface in addition to the first memory element or the second memory element.

  By using the first and second connection information whose third connection information and the fourth connection information or the output interface are also output targets, the input target and the output target constitute a circuit of the input interface and the output interface. The reconfiguration information can be generated by the control unit.

  An example of a plurality of processes is a process of a plurality of nodes included in an application whose function is indicated by a tree structure in which a plurality of nodes are connected. The control unit can determine the processes to be executed from among a plurality of processes and their order according to the tree structure of the application to be processed. For this reason, in this data processing apparatus, a function given by a tree structure program having an arbitrary configuration can be executed by a dedicated circuit. In addition, an application whose function is shown in the tree structure is automatically generated, or the application whose function is shown in the changed tree structure is changed to hardware while autonomously or otherwise dynamically changing the tree structure. It is possible to execute on a base.

Another aspect of the present invention provides reconfiguration information including connection information of a plurality of elements in order to reconfigure a data processing apparatus having a reconfiguration unit including a memory element in a circuit included in the reconfiguration unit. Is controlled by a control unit that outputs. The method includes the following steps.
In order to execute a plurality of processes in order from the connection information library in which the first connection information and the second connection information described above are stored, the memory element that is the output target in the previous process is the input target. Select connection information.
-Output reconfiguration information including the selected connection information.

  It is desirable that the connection information library further stores the above-described third connection information and fourth connection information. Moreover, it is desirable that the first connection information and the second connection information are also output targets of the output interface.

Furthermore, if the plurality of processes are processes of a plurality of nodes included in an application whose function is indicated by a tree structure, the method preferably further includes the following steps.
-Decide the process to be executed from among multiple processes and their order according to the tree structure of the application to be processed.

  The connection information library further includes fifth connection information whose input is the third memory element and whose output is the fourth memory element, and whose input is the fourth memory element. Other connection information may be stored including the sixth connection information whose output is to be output. A plurality of circuits for executing two or more processes are simultaneously configured in the reconfiguration unit, and the control unit can output reconfiguration information for executing the plurality of processes in parallel.

  Another aspect of the present invention provides a program or a program product for controlling a data processing apparatus having a reconfiguration unit including a memory element by a control unit that outputs reconfiguration information including connection information of a plurality of elements. It is. The program executes a plurality of processes in order from the connection information library in which the first connection information and the second connection information described above are stored. Selecting connection information whose input is to be input, and outputting reconfiguration information including the selected connection information.

  FIG. 1A shows an example of a reconfigurable device. This device 1 is a semiconductor integrated circuit device called DAPDNA developed by the applicant of the present application. The device 1 includes a RISC core module 2 called DAP and a dynamic reconfigurable data flow accelerator 3 called DNA. In addition to DAP2 and DNA3, the device 1 has a DNA4 direct input / output interface 4, a PCI interface 5, an SDRAM interface 6, a DMA controller 7, and other peripheral devices 8, and a high speed for connecting them. Switching bus (internal bus) 9. The DAP2 includes a debug interface 42a, a RISC core 42b, an instruction cache 42c, and a data cache 42d. The DNA 3 is used to reconfigure the PE matrix 10 by changing the function and / or connection of the PE matrix 10 in which 376 PEs (PEs, processing elements) are two-dimensionally arranged and the PEs included in the PE matrix 10. And a configuration memory 19 in which configuration data 18 is stored.

  The configuration memory 19 has a plurality of banks. For example, as shown in FIG. 1B, the PE matrix 10 includes a first function (data flow, circuit design) 17a by configuration data 18 stored in the foreground bank. Further, the second function 17b and the third function 17c are configured by configuration data stored in different background banks, respectively. By switching the bank of the memory 19, the PE matrix 10 is reconfigured with the second function 17b or the third function 17c instead of the first function 17a. The reconstruction of the PE matrix 10 is dynamically performed in one cycle (clock cycle), for example. Thus, the PE matrix 10 is a reconfiguration unit including a plurality of elements for configuring a circuit and internal wirings for connecting these elements. By changing the connection of the elements by the internal wirings, the PE matrix 10 10 can be reconfigured.

  FIG. 1C is an example in which a circuit is reconfigured in the PE matrix 10. A plurality of functions (subfunctions) obtained by time-division of an application such as an MPEG decoder are reconfigured in the PE matrix 10 by time-division, and the functions of the MPEG decoder are provided by a dedicated circuit (dedicated hardware). By using such a device, an application requiring a large amount of hardware resources can be executed with a small amount of hardware resources using the device 1 which is a reconfigurable data processing apparatus.

  FIG. 1 (d) is another example of configuring a circuit in the PE matrix 10. In order to execute applications having different playback methods, the PE matrix 10 can be reconfigured so that a plurality of functions are realized. Through such use, many applications can be executed using the common hardware (device) 1. Since this device 1 can be implemented by switching a large number of functions at the data flow level (data path level, hardware level) instead of the program level (instruction level), processing can be performed at a speed comparable to that of dedicated hardware. Can do.

  FIG. 2 shows an enlarged arrangement of the PE matrix 10. The processing elements PEs are arranged so as to constitute a 16 × 24 matrix as a whole. As shown in FIG. 3, some of the PEs occupy the space of two PEs, and as a whole, 376 PEs are actually arranged in the PE matrix 10, but this is reflected in FIG. Not done. These PEs are further divided into six groups each consisting of 8 × 8 PEs. These groups are referred to as segments S, and segments S0 to S5 are arranged in order from the upper left to the lower right of the PE matrix 10. The PEs included in each of the segments S0 to S5 are connected by an intra segment connection that can transmit and receive data within a delay of one cycle. Also, among the segments S0 to S5, adjacent segments are connected by an intersegment connection 22 via a delay element described later.

  FIG. 3 shows a specific arrangement example of PEs included in the PE matrix 10. Among PEs shown in FIG. 3, PEs beginning with “EX” are called “EXE elements” and are arithmetic elements including arithmetic operations, logical operations, and 2-input comparison functions. “EXC” has a CMPSB instruction, “EXF” has a FF1 instruction, “EXM” has a multiplication instruction, “EXR” has a BREV instruction, and “EXS” has a BSWAP instruction It also includes a calculation function unique to each type.

  PEs beginning with “DL” are delay elements, and can each set a delay of 1-8 clocks. “DLE” is for data delay within a segment, “DLV” is for data transmission / reception between vertical segments, “DLH” is for data transmission / reception between horizontal segments, and “DLX” is It is an element for data transmission / reception between vertical and horizontal segments.

  The PE displayed as “RAM” is an element (memory element) used as an internal memory of DNA. The PE displayed as “LDB” is a DNA internal buffer for data input. The PE displayed as “STB” is a DNA internal buffer for data output. The PE displayed as “C16E” is an address generation element for the DNA internal buffer. The PE displayed as “C32E” is an address generation element for the external memory space. The PE displayed as “LDX” is an element for data input from the DNA direct I / O. The PE displayed as “STX” is an element for outputting data to the DNA direct I / O. In the PE matrix 10, LDB and LDX can be used as input interfaces for inputting data from outside, and STB and STX can be used as output interfaces for outputting data to the outside.

  FIG. 4 is a block diagram showing a schematic configuration of an EXE element (“EXM”) as an example of PE. The EXM element includes an ALU 11a, a MUL (16 × 16) 11b, an FF 11c, and the like. This EXM element is configured to execute an arithmetic operation, a logical operation, a two-input comparison function, a multiplication instruction, or a compound instruction by using configuration data 18 stored in the configuration memory 19 of DNA3. Can be configured. In addition, since a plurality of FFs 11c are built in, it is possible to control the latency from data input to output to the element PE, and in a configuration where the number of delay elements (DLE) is insufficient, the function as a delay element. It is also possible to set

  FIG. 5 is a block diagram showing a schematic configuration of a RAM element (“RAM”) as another example of PE. This RAM element is a data storage memory element, which is a 16 KB (32 bits × 4096 words) RAM module 12a, an address input address register (FF) 12b, a latch 12c, and a data input write data register (FF). ) 12d, a latch 12e, and a read data register (FF) 12f for data output. The read / write control of the RAM module 12a is performed by the token value input together with the address data and / or read data. From the address input to the read data output, it is possible in about 3 clock cycles like the EXE element, and data input / output is possible with the same latency as other types of PE included in the PE matrix 10. is there. This RAM element has a 32-bit mode, a dual-port 32-bit mode, a FIFO mode, a 16-bit mode, an 8-bit mode, and an FSM (feedback state mode) based on configuration data 18 stored in the configuration memory 19 of DNA3. Can be configured to input and / or output data.

  The EXE element and the counter element C16E and / or C32E can be used to generate the access address of the RAM element, and can be input to the RAM element through the routing matrix (matrix bus) of the PE matrix 10. Therefore, input / output to / from the RAM element can be controlled by a circuit reconfigured in the PE matrix 10.

  The PE matrix 10 includes a plurality of PEs and a routing matrix (wiring group) 20 for connecting them. The routing matrix 20 is used to connect the first level wiring group (first level routing matrix, intraconnect) 21 for connecting the PEs in the segment S and the adjacent segment S via the delay element. And a second level wiring group (second level routing matrix, interconnect) 22. Connection of PEs by the routing matrix 20 can be controlled by the configuration data 18. Therefore, the PE matrix 10 has different circuits (data paths) by changing the function of each of the plurality of PEs and / or changing at least part of the connection of the routing matrix 20 according to the configuration data 18. , Data flow) can be reconfigured.

  FIG. 6 shows an example of the configuration of the first-level wiring group 21 for connecting the PEs inside the segment S. The first level routing matrix 21 includes 128 vertical buses 23 and 64 horizontal buses 24 for connecting 8 × 8 PEs included in the segment S0. The vertical buses 23 are divided into 16 groups, and two V-buses 23x and 23y each including eight buses are paired and arranged along the vertical column of PEs on both sides of the column. Has been. The horizontal buses 24 are divided into eight groups, and H-buses 24 each including eight buses are arranged along the horizontal rows (lines) of the PEs. The V-buses 23x and 23y are provided with 8-1 bus selectors (multiplexers, MUX) 25 corresponding to the respective PEs, and data can be input to the respective PEs.

  The H-bus 24 is provided with 8-1 bus selectors (multiplexers, MUX) 26 corresponding to the intersections of the H-bus 24 and the V-buses 23x and 23y. Therefore, one data set can be output from one H-bus 24 to one V-bus 23 x or 23 y intersecting with the H-bus 24. The reverse is also possible. Each bus included in the H-bus 24 is connected to the output of the PEs of that line. Therefore, PEs included in the segment S can be connected through the V-buses 23x and 23y and the H-bus 24. Data can be connected within the range that can be connected by the first level bus 21 including the V-buses 23x and 23y and the H-bus 24, that is, within one cycle (one clock) between the PEs in the segments S0 to S5. Can send and receive. Therefore, in terms of timing, for example, all PEs included in the segment S0 are equivalent. For this reason, in order to configure a circuit within the same segment, no matter which PE is selected and assigned a function, there is no need to consider the timing. In terms of timing, PEs in the segment are used. The predetermined circuit can be freely arranged and wired.

  FIG. 7 shows the configuration of the second level routing matrix 22. In FIG. 7, the connection elements DLH included in the adjacent segments S <b> 1 and S <b> 4 are connected by the second-level routing matrix 22. Each DLH is connected to a first level routing matrix 21 within each segment S1 and S4. Therefore, the PE included in the segment S1 and the PE included in the segment S4 can be connected via the second level routing matrix 22. The connection delay element DLH functions as an interface of a bus included in the first level routing matrix 21. Therefore, the buses included in the first level routing matrix 21 can be used independently for each segment. On the other hand, when it is necessary to input / output data between segments, it is necessary to input / output data via a plurality of FFs included in the connection delay element DLH, and there is a delay of two cycles or more in synchronization with the clock. Newly join.

  In this way, when PEs are connected using only the first level routing matrix 21, it is guaranteed that PEs are connected within a range of one cycle (first delay), and timing verification is unnecessary. It is. On the other hand, when connecting PEs via the second level routing matrix 22, a delay of two cycles or more is added. The delay when connecting via the second level routing matrix 22 depends on the setting of the delay element DLH. For example, by controlling the delay amount of DLH, a signal that uses the second routing matrix 22 twice and a signal that is used once can be synchronized. The same applies when adjacent segments S0 to S5 are connected via other connection delay elements DLV and DLX.

  For this reason, a circuit distributed to a plurality of segments S0 to S5, that is, a circuit across the segments, needs to be adjusted or reexamined during or after the placement and routing. As a result, it may be required to add delay elements or adjust the delay of the delay elements. Therefore, it is preferable to minimize the use of the second level routing matrix 22 when placing and wiring circuits in the PE matrix 10.

  FIG. 8 shows an example of an application whose function is shown by a tree structure. The tree structure indicates a structure in which nodes are connected in a line or branched. This application 30 is an image process (image filter) in which a plurality of processes are combined to form a tree structure, and the tree structure is optimized based on conditions such as an input image and an object to be extracted. . The optimization technique is a technique called GAGP described above, and is genetic programming (GP) devised based on the genetic algorithm (GA). The optimization method for finding the tree structure is not limited to GAGP, and may be another optimization method such as a method based on an immune algorithm or a simulated annealing method.

  The image processing application 30 having a tree structure includes processes 31 of a plurality of nodes arbitrarily combined, and the processes 31 of these nodes are executed in the combined order. The node processing 31 is not limited to the 1-input 1-output processing, and may be multi-input 1-output or multi-input multi-output. In this example, the 2-input 1-output processing 31 is included. When the 1-input 1-output process (node) 31 is connected, the output of the previous process 31 becomes the input of the next process 31. When the 2-input 1-output process is the node process 31, two branches (processing paths) intersect to form one branch (processing path) and be connected to the next node. That is, the output of the previous two processes 31 becomes the input of the next process 31.

  In the image processing application 30, the processing 31 of each node having a tree structure is an image filter (filter unit) whose conversion function is limited to some extent according to the purpose of image processing. The filter unit with one input and one output includes an average value filter (−), a maximum value filter (M), a minimum value filter (m), a Sobel filter (d), a black region edge extraction Laplacian filter (E), and a bright region. Edge extraction Laplacian filter (e), filter (X) that brightens those whose divided region area is smaller than the average value, filter (x) that brightens those whose divided region area is larger than the average value, bright pixels (for example, above average) A filter (T) that selects black with a large gradation value (other), a filter (t) that makes black otherwise, a filter (t) that selects a dark pixel (for example, a smaller gradation value than the average) and makes others bright, and a high-pass filter (F, For example, discrete cosine transform, cut low frequency component, and inverse discrete cosine transform), low pass filter (f, eg, discrete cosine transform, high frequency component Cut and inverse discrete cosine transform), tone value inversion processing filter (i), linear transformation filter (H), binarization processing filter by average value (N), binary processing filter by values obtained by analysis processing (N) etc. can be mentioned.

  The filter unit with two inputs and one output includes logical sum (L), logical product (l), algebraic sum (A), algebraic product (a), limit sum (B), limit product (b), and differential filter (D ) And the like.

  FIG. 9 shows an example in which the application 30 whose function is shown in the tree structure is executed by the DAPDNA 1 shown in FIG. In this example, the DAP 2 includes a function as the reconstruction control unit 2a, and the PE matrix 10 is a reconstruction area. The reconfiguration control unit 2a outputs to the configuration memory 19 one set (node unit) circuit configuration (reconfiguration information, configuration data) 18 for executing the processing 31 of each node according to the tree structure. A circuit for executing the node processing 31 is configured in the PE matrix 10. Hardware information 39 for executing the application 30 including the configuration data 18 for instructing a circuit configuration for executing the processing 31 of each node is designed (generated) in advance according to the tree structure of the application 30. It is stored in a DRAM (SDRAM) 6.

  In the DAPDNA 1, circuit configuration data 18 for executing the processing 31 of the next node can be stored in the bank of the configuration memory 19. Therefore, the PE matrix 10 can be reconfigured in approximately one clock cycle according to the tree structure. Therefore, an application whose function is shown in a tree structure can be executed at high speed using a dedicated circuit. Furthermore, by changing the configuration data 18, an application having a different tree structure can be mounted on the DAPDNA 1, so that a plurality of types of tree structure applications suitable for an image input situation and / or an extraction target can be appropriately executed on one DAPDNA 1. .

  FIGS. 10A and 10B show different examples in which the application 30 whose functions are shown in a tree structure is executed by the DAPDNA 1. In the example shown in FIG. 9, the circuit configured in the PE matrix 10 inputs and outputs data using the DRAM 6 of the DAPDNA 1 as a work area. On the other hand, in the example shown in FIGS. 10A and 10B, the circuit configured in the PE matrix 10 inputs and outputs data using the RAM element of the PE matrix 10 as a work area.

  In the image processing application 30 having a tree structure, the processing of each node is repeatedly performed by reading, converting, and outputting pixel data included in image data to be processed. Therefore, data is frequently input / output from / to the work memory area. In the example shown in FIG. 9, a work area 6 a is provided in the DRAM 6. Since the DRAM 6 is a memory included in the DAPDNA 1, data can be input and output from the circuit configured in the PE matrix 10 at high speed.

  However, several procedures are required to input or output data between the PE matrix 10 and the DRAM 6. For example, when data is supplied from the DRAM 6 to the PE matrix 10, first, the internal bus 9 connecting the PE matrix 10 and the DRAM 6 is opened for accessing the PE matrix 10, and an address for memory access is assigned from the PE matrix 10. Output. Thereafter, predetermined data is output from the DRAM 6 to the bus 9 and supplied to the PE matrix 10. The data output to the bus 9 is transferred to a circuit configured in the PE matrix 10 so as to function as a node (image filter) via an LDB element serving as an internal buffer for data input in the PE matrix 10. Entered. When outputting data processed by a circuit configured in the PE matrix 10, it is necessary to go through substantially the same procedure.

  The cycle consumed for such data input / output is the same in a general-purpose processor such as RISC that sequentially performs processing according to the description of the program. Therefore, in DAPDNA1, a circuit for executing different processing 31 depending on the node can be reconfigured in the PE matrix 10 in one clock cycle, whereas data input / output consumes a large number of clock cycles, so that the circuit is reconfigured. Doing so will not lead to delays in data processing. Conversely, once the circuit is configured in the PE matrix 10, the node 30 is executed by the application 30 using a dedicated circuit (hardware). For this reason, in DAPDNA1, the process proceeds at a higher speed than when the application 30 is executed by controlling a general-purpose processor.

  Further, in the example shown in FIGS. 10A and 10B, filter circuits (processing circuits) 61 and 62 having RAM elements as input / output targets are configured in the PE matrix 10. These filter circuits 61 and 62 include arithmetic elements (EXE) arranged in the PE matrix 10, are circuits for realizing a function as a predetermined filter, and may include a RAM element. In FIG. 10A, the PE matrix 10 is configured with a filter circuit 61 having the first RAM element (RAM # 1) as an input target and the second RAM element (RAM # 2) as an output target. . In FIG. 10B, a filter circuit 62 is configured with the second RAM element (RAM # 2) as an input target and the first RAM element (RAM # 1) as an output target. In this way, the RAM # 2 that is the output target of the Kth (fifth) processing circuit 61 shown in FIG. 10A is replaced with the (K + 1) th (sixth) shown in FIG. By setting the processing circuit 62 as an input target, it is possible to execute a plurality of processes 31 connected in a tree structure only by data transfer inside the PE matrix 10. Therefore, it is not necessary to input data via the internal bus 9 and the LDB element of the DAPDNA 1, and the procedure required to access the working memory is simplified. Therefore, the processing time required for data input / output is reduced in the node processing 31, and the application 30 can be executed at higher speed in the DAPDNA1.

  FIG. 11 is a block diagram of a data processing apparatus as an example of an embodiment of the present invention. The data processing device 50 is realized using DAPDNA1. The data processing device 50 has a PE matrix 10 that is a reconstruction unit (reconstruction area). This PE matrix 10 includes a plurality of elements (PE) for configuring a circuit and an internal wiring 20 for connecting these PEs. By changing the connection of the plurality of PEs by the internal wiring 20, the PE matrix 10 The circuits included in the reconstruction unit 10 can be reconfigured. Further, the data processing device 50 includes a reconfiguration control unit 2a that outputs reconfiguration information (configuration data) 18 including connection information of a plurality of PEs in order to reconfigure a circuit mounted on the PE matrix 10. . In this data processing device 50, the reconfiguration control unit 2a is provided by the DAP2.

  As described above, the PE matrix 10 includes a plurality of types of PEs including an arithmetic element (EXE) that is a PE for arithmetic operation and a RAM element (RAM) for internal memory. Then, by changing the connection of the internal wiring 20 including the first level wiring 21 and the second level wiring 22, a predetermined RAM element can be set as a processing circuit input target or an output target including EXE. It is.

  In the data processing device 50, a connection information library 55 including a plurality of sets of connection information (connection data) 56 and tree structure information 35 are stored in the DRAM 6. In the connection information library 55, the first memory element (RAM # 1) is set as an input target for some of the tree-structured node processes 31, particularly for each of the 1-input 1-output processes, and the second memory element The first connection information for configuring the first processing circuit whose output target is (RAM # 2) and the second memory element (RAM # 2) are input targets, and the first memory element (RAM # 2) is input. The second connection information for configuring the second processing circuit whose output target is 1) is stored. Accordingly, when the reconfiguration control unit 2a sequentially executes the node processing 31 in accordance with the tree structure information 35, the reconfiguration control unit 2a uses the connection information library to input connection information for the memory element that is the output target in the previous processing. By selecting from 55 and outputting the configuration data 18 including the selected connection information to the configuration memory 19, it is possible to sequentially configure a circuit for executing the tree-structured application 30 in the PE matrix 10. The connection information (connection information set or piece (connection data set)) 56 corresponding to the processing 31 of each node included in the connection information library 55 is set in the PE as well as information on PE connection. All necessary information as configuration data 18 may be included.

  FIG. 12 shows several types (sets, pieces) of the connection information 56 included in the connection information library 55. The type 1 connection information 56a is a first processing circuit 61 for configuring the first processing circuit 61 having the first RAM element (RAM # 1) as an input target and the second RAM element (RAM # 2) as an output target. 1 connection information. The connection information 56a is configured to include a processing circuit 61 that outputs not only the RAM element but also the STB that is the PE of the output interface. If the processing result of the first processing circuit 61 needs to be stored in the work area 6 a of the DRAM 6 from the PE matrix 10, the processing result is sent from the STB to the DRAM 6 via the bus 9.

  The type 2 connection information 56b is second connection information for configuring the second processing circuit 62 whose input is RAM # 2 and whose output is RAM # 1. The connection information 56b is also configured to include a processing circuit 62 that outputs the STB that is the PE of the output interface.

  The type 3 connection information 56c is third connection information for configuring the third processing circuit 63 whose input target is the LDB which is the PE of the input interface and whose output target is the RAM # 1. The connection information 56c is also configured to have a processing circuit 63 that outputs an STB that is the PE of the output interface.

  The type X connection information 56d is connection information for configuring a 2-input 1-output filter circuit in the PE matrix 10, and is a process in which two LDBs are input targets and RAM # 1 and STB are output targets. Connection information for configuring the circuit 69. The same data is output to RAM # 1 and STB.

  For the 1-input 1-output filtering process 31 that may be included as a node of the tree-structured image processing application 30, type 1 to type 3 connection information is prepared in the connection information library 55 for each process. ing. For example, three types of connection information 56 of type 1 to type 3 are stored in the library 55 as connection information for configuring the average value filter in the PE matrix 10. The circuit configured in the PE matrix 10 by these three types of connection information 56 is for providing a function as an average value filter, and provides the same function except for input and output. Further, the three types of connection information 56 are optimized so that the respective processing circuits are connected to different input targets and different output targets, and the number of PEs consumed to provide a function as a filter. Is generated to be as small as possible. For example, arithmetic filters that function as selectors for switching inputs and delay elements, in particular, delay elements introduced into wiring straddling segments, are reduced, and complex filters that effectively use PEs included in the PE matrix 10 are used. Be ready for processing. Further, the processing circuit configured in the PE matrix 10 has a simple configuration so that the time required for processing is shortened.

  As for the 2-input 1-output process, it is possible to prepare a plurality of types of connection information as in the 1-input 1-output process. However, in the image processing application 30, in the 2-input 1-output filter processing, at least one of the image data is image data of different frames. For this reason, the input of the 2-input 1-output filter often receives data supplied from an external memory (DRAM) 6 or a memory outside the DAPDNA 1. Further, if the first and second RAM elements have two inputs, there is a possibility that the output RAM element may be limited in the process ahead of the two-input process. For one-output processing, data is input from an external memory. Therefore, the filtered data input to the 2-input 1-output process is once output to the work area 6 a of the DRAM 6.

  The connection information 56 stored in the connection information library 55 is not limited to that described above. The connection information 56a to 56c of types 1 to 3 prepared for the 1-input 1-output process includes an STB that is an output interface in addition to the RAM element as an output target. On the other hand, it is possible to independently prepare connection information in which the output target is only the RAM element and connection information in which the output target is only the output interface. For example, the connection information library 55 stores the fourth connection information for configuring the fourth processing circuit having the first RAM element or the second RAM element as an input target and the STB as an output interface as an output target. Can be kept.

  Furthermore, it is effective to prepare in the library 55 connection information for the third RAM element and the fourth RAM element, which are different from the first and second RAM elements, to be input or output. . When the scale of the processing circuit is sufficiently small, a processing circuit whose input / output targets are the first and second RAM elements and a processing circuit whose input / output targets are the third and fourth RAM elements are connected to PE. It is possible to simultaneously generate the matrix 10 and execute these processes in parallel. For example, the application 30 can be executed at higher speed by executing the processing of the nodes of the branches of the tree structure of the application 30 in parallel.

  FIG. 13 shows the operation of the reconfiguration control unit 2a when executing the application 30 having a tree structure in the data processing apparatus 50 using a flowchart. In step 70, information about the tree structure of the application 30 (hereinafter “tree structure”) 35 is acquired from the DRAM 6. In step 71, connection information 56 of the first node # 0 (process # 0 in FIG. 8, gradation value inversion process) of the tree structure 35 is acquired from the connection information library 55. Since node # 0 is the first process, it is necessary to acquire image data from the DRAM 6. Therefore, in step 71, the control unit 2a acquires the type 3 connection information 56c of the connection information in order to configure the processing circuit for performing the gradation value inversion processing in the PE matrix 10. In step 72, the control unit 2a generates the configuration data 18 based on the connection information 56c, and outputs the configuration data 18 to the bank # 1, for example, in the configuration memory 19. In step 73, the control unit 2a moves the configuration data 18 of the bank # 1 in the configuration memory 19 to the foreground bank. As a result, a processing circuit that performs gradation value inversion processing on the PE matrix 10 is configured, and the processing circuit is configured to input the LDB and the output target of the RAM # 1, and the image data is input from the external memory. A process of outputting the image data subjected to the gradation value inversion process to the RAM # 1 is started.

  While the processing is being performed in the PE matrix 10, the control unit 2a further transfers the connection information 56 of the next node # 1 (processing # 1, FIG. 8, average value processing) to the connection information library in step 74. 55. Node # 1 is the second process, and the output target of the first process is RAM # 1. Therefore, the control unit 2a acquires the type 1 connection information 56a among the connection information for configuring the processing circuit for performing the average value processing in the PE matrix 10. In step 75, the control unit 2a generates the configuration data 18 based on the connection information 56a, and outputs the configuration data 18 to the bank # 1, for example, in the configuration memory 19.

  In step 76, the control unit 2a waits for the end of the current process configured in the PE matrix 10, that is, the process # 0. In step 77, the completion of all the processes of the tree structure 35 is confirmed. If not, the configuration data 18 of the bank # 1 in the configuration memory 19 is moved to the foreground bank in step 78. As a result, a processing circuit that performs average value processing and that has RAM # 1 as an input target and RAM # 2 as an output target is configured in the PE matrix 10. Then, the image data that has been subjected to the gradation value inversion processing is read from the RAM # 1 and the image data that has been subjected to the average value processing is output to the RAM # 2.

  If it is determined in step 79 that the process of the next node remains in the tree structure 35, the process returns to step 74, and connection information 56 suitable for performing the process of that node is acquired from the connection information library 55. In step 79, if the process of the next node does not remain, the process returns to step 76. When the current process is completed, the circuit for processing the last node is re-executed by the configuration data 18 output to the configuration memory 19. Constitute.

  Since the configuration memory 19 of the DAPDNA 1 has a 4-bank configuration, configuration data 18 for configuring the next processing circuit in the PE matrix 10 can be output in advance to the banks # 2 and # 3. Further, the function of the reconfiguration control unit 2a can be provided as a program (program product) loaded in the RISC type DAP 2, and can be provided by being recorded in an appropriate recording medium such as a ROM.

  In this data processing device 50, in order to configure the processing circuit of the processing # 2 in the PE matrix 10, the connection information 56b of type 2 whose input is the RAM # 2 that is the output target of the processing circuit of the processing # 1. Is selected. In the node before the 2-input 1-output node, the output target must be the work area 6 a of the DRAM 6. Therefore, in order to configure the processing circuit of the processing # 3 in the PE matrix 10, the type 1 connection information 56a for which the RAM # 1 is input is selected, and the data processed by the processing circuit 61 is transmitted via the STB. It is output to the DRAM 6. In order to configure the processing circuit # 4 with two inputs and one output in the PE matrix 10, the type X connection information 56d with two LDBs as input targets is selected, and the data processed by the processing circuit 69 is Output to RAM # 1.

  As described above, in the data processing device 50, when the tree structure 35 is given, the tree structure 35 is analyzed, and processing suitable for executing the processing of the node according to the order of the nodes included in the tree structure 35. Connection information 56 for configuring the circuit is selected from the connection information library 55, and the processing circuit is configured in the PE matrix 10. Therefore, even if the application 30 has a different tree structure 35, the application 30 can be executed by providing the data processing device 50 with the tree structure information. For this reason, it is not necessary to generate all the circuit configurations for executing the applications in advance for each application having a different tree structure and generate the configuration information as configuration information.

  Furthermore, even if the tree structure 35 is mutated due to an autonomous factor or an external factor inside the data processing device 50, a circuit for processing each node according to the mutated tree structure 35 is provided. The PE matrix 10 can be configured.

  FIG. 14 is a block diagram of a different data processing apparatus according to the embodiment of the present invention. The data processing device 51 is realized by using the DAPDNA 1 and outputs the configuration data 18 for reconfiguring the PE matrix 10 which is a reconstruction unit (reconstruction area) and the circuit mounted on the PE matrix 10. It has a reconfiguration control unit 2a. The function of the reconfiguration control unit 2a is provided by DAP2. Further, the DAP 2 provides functions as a candidate tree structure generation unit 2c, a processing order output unit 2d, and a candidate tree structure evaluation unit 2b.

  The candidate tree structure generation unit 2c generates image processing whose function is indicated by the tree structure according to the rules of the genetic algorithm. The DRAM 6 is provided with a filter library 37 and stores information 36 of each filter that can be adopted as a tree-structured node that can be used by the candidate tree structure generation unit 2c. The DRAM 6 includes an image data storage unit 66. The image data storage unit 66 includes initial image data 66a that is a target of image processing in a tree structure, reference image data 66b that provides a reference for evaluation, and evaluation data. The target image data 66c is stored. The image data 66c to be evaluated by the evaluation unit 2b is a result of processing the initial image data by image processing having a tree structure generated by the candidate tree structure generation unit 2c. The tree structure 35 that is highly evaluated by the evaluation unit 2b is registered in the DRAM 6 as an application 30 used for image processing in the data processing device 51, and is used for processing image data input from the outside.

  The processing order output unit 2d extracts, by the candidate tree structure generation unit 2c, the processing 31 of each node included in the candidate tree generated according to the rules of the genetic algorithm and the order thereof, and supplies the extracted processing to the reconstruction control unit 2a. To do. Similar to the data processing device 50 described above, the reconfiguration control unit 2a selects appropriate connection information in accordance with the information from the sequential output unit 2d, and configures an appropriate circuit in the PE matrix 10.

  As described above, when an arbitrary tree structure 35 is generated by the candidate tree structure generation unit 2c, the data processing device 51 time-divides a circuit for performing image processing including the tree structure 35 into the PE matrix 10. Can be reconfigured. For this reason, according to the rules of the genetic algorithm, it is possible to execute a process for generating a tree structure of image processing for obtaining an optimum processing result by using a circuit dedicated to processing of nodes included in the tree structure. Therefore, it is possible to obtain a tree structure for image processing that can obtain an optimum result in a short time.

  FIG. 15 shows different examples of circuits configured in the PE matrix 10 by the connection information 56. The connection information 56e for configuring the circuit 80 corresponds to type 1 connection information, but in this example, output to the STB is omitted. RAM # 1 and RAM # 2 do not have to be a single element, but may be a data read circuit including several RAM elements. The address arbitration circuits 80a and 80b can be configured using C16E and / or C32E, which are counter elements, and an EXE element. The same applies to the following circuits.

  FIG. 16 is a further different example of a circuit configured in the PE matrix 10 by the connection information 56. The connection information 56f for configuring the circuit 81 corresponds to type 1 connection information, but in this example, output to the STB is omitted. The filter processing circuit 61 includes four parallel processing routes (data paths). Therefore, this circuit 81 includes four processing circuits whose inputs are RAM # 1-1 to RAM # 1-4 and whose outputs are RAM # 2-1 to RAM # 2-4. An example of a filter circuit that performs four parallel processes is the average value filter processing circuit 89 shown in FIG. This average value filter calculates and outputs the average value of the target pixel and the surrounding pixels (eight pixels). In the circuit 89 shown in FIG. 17, the average value processing with 4 pixels as the target pixel is performed in 4 parallel. In the circuit 89 shown in FIG. 17, 8 bits × 4 pixels are packed into 32-bit data and input / output, and there is one RAM element to be input and one output.

  FIG. 18 is a further different example of a circuit configured in the PE matrix 10 by the connection information 56. The connection information 56g for configuring the circuit 82 corresponds to type 1 connection information, but in this example, output to the STB is omitted. The four RAM # 1-1 to RAM # 1-4 to be input are serial-converted and read by the selector 82a. In addition, RAM # 2-1 to RAM # 2-4 to be output are written by parallel conversion by the selector 82b.

  FIG. 19 is a further different example of a circuit configured in the PE matrix 10 by the connection information 56. The connection information 56h for configuring the circuit 83 corresponds to connection information of type 1, but in this example, output to the STB is omitted. The four RAM # 1-1 to RAM # 1-4 to be input are serially converted and read by the selector 82a, and are parallel to the RAM # 2-1 to RAM # 2-4 to be output. The data is written in.

  In the above, an application that performs image processing is described as an example of an application whose function is indicated by a tree structure. The application whose function is indicated by the tree structure is not limited to image processing, and may be audio processing. Furthermore, applications that can be executed in the data processing apparatus are not limited to applications having a tree structure. If the function of the application is given as a set of processes that are combined to some extent with data input and output, and the order of those processes is determined, the reconfiguration control unit selects connection information according to the order. By outputting the configuration data, the application can be executed by a dedicated circuit configured in the reconfiguration unit.

FIG. 1 (a) shows a schematic configuration of an example of a reconfigurable device, FIG. 1 (b) shows a schematic of a PE matrix, and FIGS. 1 (c) and 1 (d) show a PE matrix. The state of dynamic reconfiguration is shown. The figure which shows the arrangement | sequence of PE matrix. The figure which shows the type of PE arrange | positioned at PE matrix. The block diagram which shows the structure of one type of EXM of PE. The block diagram which shows the structure of one type of RAM of PE. The figure which shows the wiring (intra segment wiring) in a segment. The figure which shows the wiring (intersegment wiring) between segments. An application whose functions are represented by a tree structure. The block diagram which shows an example of the data processing apparatus containing the area | region which can be reconfigure | reconstructed. 10A and 10B show another example in which a filter circuit is configured in a reconfigurable region. The block diagram which shows one data processor of embodiment. An example of connection information included in the connection information library. The flowchart which shows operation | movement of a reconstruction control unit. The block diagram which shows the other data processing apparatus of embodiment. Another example in which a filter circuit is configured in a reconfigurable region. Another example in which a filter circuit is configured in a reconfigurable region. The circuit example of an average value filter. Another example in which a filter circuit is configured in a reconfigurable region. Another example in which a filter circuit is configured in a reconfigurable region.

Explanation of symbols

1 Reconfigurable Device 2a Reconfiguration Control Unit 10 PE Matrix (Reconfiguration Unit)
50, 51 Data processing device 55 Connection information library, 56 Connection information

Claims (9)

A reconfiguration unit including a plurality of elements for configuring a circuit and an internal wiring for connecting the plurality of elements, wherein the circuit is changed by changing connection of the plurality of elements by the internal wiring. A reconfigurable reconfigurable unit;
A data processing device having a control unit that outputs reconfiguration information including connection information of the plurality of elements to reconfigure the circuit of the reconfiguration unit,
The plurality of elements include a plurality of calculation elements for executing at least one kind of calculation and a plurality of memory elements, and by changing connection of the internal wiring, at least one of the plurality of memory elements Can be an input object or an output object of a processing circuit including at least one of the plurality of arithmetic elements,
The data processing device further includes for each of the processing of a plurality of processes involving the input and output of data, the first memory element of the input object, performs the respective processes as an output target of the second memory element a first connection information for configuring the processing circuit, and the second input of the memory element target, for configuring the processing circuit for performing the respective processes in the output target the first memory element A connection information library storing second connection information;
In order to execute the plurality of processes in order, the control unit selects, from the connection information library, connection information whose input target is a memory element that is an output target in the previous process, and the selected connection information A data processing device that outputs reconstruction information including 2. The reconfiguration unit according to claim 1, wherein the reconfiguration unit includes an input interface and an output interface, and by changing connection of the internal wiring, the input interface is set as an input target of the processing circuit, and the output interface is set as the processing circuit. Can be output,
The connection information library further includes, for each of the plurality of processes, a processing circuit having the input interface as an input target and the first memory element or the second memory element as an output target. Third connection information and fourth connection information for configuring a processing circuit having the first memory element or the second memory element as an input target and the output interface as an output target are stored. A data processing device.   3. The output information according to claim 2, wherein the first connection information is output from the output interface in addition to the second memory element, and the second connection information is output from the output interface in addition to the first memory element. A data processing apparatus, which is a target, and wherein the third connection information targets the output interface in addition to the first memory element or the second memory element.   4. The plurality of processes according to claim 1, wherein the plurality of processes are processes of a plurality of nodes included in an application whose function is indicated by a tree structure in which a plurality of nodes are connected. A data processing device that determines processing to be executed from among the plurality of processings and their order according to the tree structure. A reconfiguration unit including a plurality of elements for configuring a circuit and an internal wiring for connecting the plurality of elements, wherein the circuit is changed by changing connection of the plurality of elements by the internal wiring. In this method, a data processing apparatus having a reconfigurable reconfigurable unit is controlled by a control unit that outputs reconfiguration information including connection information of the plurality of elements in order to reconfigure the circuit of the reconfigurable unit. And
The plurality of elements include a plurality of calculation elements for executing at least one kind of calculation and a plurality of memory elements, and by changing connection of the internal wiring, at least one of the plurality of memory elements Can be an input object or an output object of a processing circuit including at least one of the plurality of arithmetic elements,
The method is
For each processing of a plurality of processes involving the input and output of data, the first memory element of the input object, for configuring the processing circuit for performing the respective processes as an output target second memory element of the and first connection information, and the second input of the memory element target, the second connection information and the storage for configuring the processing circuit for performing the respective processes in the output target the first memory element In order to execute the plurality of processes in order from the connection information library that has been selected, selecting connection information whose input target is a memory element that is an output target in the previous process;
Outputting reconfiguration information including the selected connection information. 6. The reconfiguration unit according to claim 5, wherein the reconfiguration unit includes an input interface and an output interface, and by changing the connection of the internal wiring, the input interface is set as an input target of the processing circuit, and the output interface is set as the processing circuit. Can be output,
The connection information library includes, for each of the plurality of processes, a third processing circuit that configures a processing circuit that uses the input interface as an input target and outputs the first memory element or the second memory element as an output target. Method of storing connection information and fourth connection information for configuring a processing circuit having the first memory element or the second memory element as an input target and the output interface as an output target .   7. The output information according to claim 6, wherein the first connection information is output from the output interface in addition to the second memory element, and the second connection information is output from the output interface in addition to the first memory element. The method, wherein the third connection information is the output target in addition to the first memory element or the second memory element. 8. The process according to claim 5, wherein the plurality of processes are processes of a plurality of nodes included in an application whose function is indicated by a tree structure in which a plurality of nodes are connected.
The method is
Determining processes to be executed from among the plurality of processes and their order according to the tree structure of the application to be processed. A reconfiguration unit including a plurality of elements for configuring a circuit and an internal wiring for connecting the plurality of elements, wherein the circuit is changed by changing connection of the plurality of elements by the internal wiring. A program for controlling a data processing apparatus having a reconfigurable reconfigurable unit by a control unit,
The control unit outputs reconfiguration information including connection information of the plurality of elements to reconfigure the circuit of the reconfiguration unit;
The plurality of elements include a plurality of calculation elements for executing at least one kind of calculation and a plurality of memory elements, and by changing connection of the internal wiring, at least one of the plurality of memory elements Can be an input object or an output object of a processing circuit including at least one of the plurality of arithmetic elements,
The program is
For each processing of a plurality of processes involving the input and output of data, the first memory element of the input object, for configuring the processing circuit for performing the respective processes as an output target second memory element of the and first connection information, and the second input of the memory element target, the second connection information and the storage for configuring the processing circuit for performing the respective processes in the output target the first memory element In order to execute the plurality of processes in order from the connection information library that has been selected, selecting connection information whose input target is a memory element that is an output target in the previous process;
Outputting reconfiguration information including the selected connection information.

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