JPS5934743A - Pattern detecting system - Google Patents

Abstract

PURPOSE:To have a fixed quantity of a pattern detector regardless of the length of a pattern which forms a data, by using an ROM memory to a storage memory for serial input data with a serial transmission system. CONSTITUTION:The serial data supplied through a data input terminal D are delivered through an output terminal P every bit via an ROM and an FF. At the same time, a fixed state number is latched to the FF from terminals D1-Dn of the ROM synchronously with the clock of a clock terminal C and then fed back to input terminals A1-An respectively. When the final bit of data is confirmed, a pattern detecting signal is transmitted from the terminal P. A pattern is written with each rise of a system without using the ROM. Thus an RAM is applicable.

Description

Detailed Description of the Invention: (1) Technical field of the invention - Turn detection method, particularly regarding a method for detecting a pattern indicating the beginning of a serial data transmission format (2) Background of the technology For example, the central control unit (CPU
) In the case of so-called serial data transmission, in which data is transferred in series between the two terminals, the CPU on the receiving side detects the first nine turns of the received serial data, and then transmits the data of the pattern that continues after the detected first turn. is treated as valid. Therefore, in the serial data transmission format, it is necessary to first display the head or detect the turn prior to data processing.

(3) Prior art and problems However, the conventional mother turn detection method was performed by the method shown in FIG. That is, the driver is driven by the clock signal applied to the terminal C.
The data input to the terminals 2+83 is stored sequentially, and the output of each renostar is sent to the associated AND gate A.
I A2 A3 is supplied, and its output is further supplied to the common anchor Ao, and from terminal l) to riJ-t or
The purpose is to obtain a pattern detection signal of "0". For example, if you set the data pattern that displays the beginning of serial data as rolloJ in advance, and rolloJ
If there are three consecutive optical head patterns, it means that serial data will be received from now on, and the data following the three consecutive optical head patterns is processed as actual valid data. In such a case, inverters 111+112...111 are connected to the 1st and 4th bits of each shift register as shown in
Connect 2. As shown in the figure, when all three leading patterns are stored in each shift register, the input power of each AND gate is all [1], so the common AND gate A. The human power is also 11'', and the leading pattern detection signal ``1'' is obtained from the output terminal P thereof.

However, in the conventional method shown in Figure 1, one
As the number of bits in a record increases, the length of the pattern to be detected also increases proportionally, so the number of bits in the register SI 5283 for data storage also increases, and if the start display butter is changed to yt-, it becomes a shift register and an AND gate. The number of inverters inserted between them must also be changed, and the ANDDART device itself also becomes more difficult. Therefore, in the conventional pattern detection method, the size and number of detection devices increase and the device configuration becomes complicated. There was a problem with that.

(4) Object of the Invention The object of the present invention is to use a ROM (Read 0
nly Memory) memory, (or RAM)
By using Random Access@Memory), the jjL of the pattern detection device can be made constant regardless of the length of the pattern constituting the data.

(5) Structure of the Invention According to the present invention, one printer can be made up of n-bits.
/In a method for detecting the pattern of each data in the real data transmission format, a unique state number is assigned to each of the above n bits, and when information on the 21st bit is input, the state corresponding to the 1st bit is determined. Holding the number, wait for the input information of the 1st and 2nd bits, repeat the same operation sequentially until the input information of the n-1th bit, and finally, when the information of the nth bit is input, A pattern detection method is provided, characterized in that a pattern detection signal is sent out.

(6) Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.

FIG. 2 is a diagram showing the configuration of an apparatus for implementing the method of the present invention. Serial data entered manually from the data input terminal is 1
Each bit is output from the output terminal P via the ROM and FF, and a fixed state number for each bit is latched by the FF synchronized with the clock from the clock input terminal C from the ROM terminals DI+...Dn. It is fed back to the input terminals Alt...An of the ROM, and when it is confirmed by this state number that it is the final bit of the data, pattern detection (number i is sent out from the output terminal P).

ROM is a read-only memory, and it is a programmer sol (p) that allows you to program the memory contents from outside after the IC is manufactured.
It is a type ROM. Also, FF is a floating point, a floating point, and data from terminal Do of the ROM and terminal D! ...D
It has the function of once latching the state number from n and feeding back the data to the output terminal P and the state number to the input terminals A1+...An of the ROM.

In a device with this configuration, one piece of serial data is 4 bits, and the first turn is displayed.
eba" in advance. Also, the state number is 1 for pattern a. 2+ for b 3f for c: Ask.

When driving the device shown in Fig. 2, input the input terminal of /ξ turn I-00tJ OJ from the data terminal to the input terminal Ao of the ROM, and clear it as #t"00'(" in the ROM. (Figure 3). Then, as shown by the broken line in Figure 3, it waits for the next data in the ()00 state.When data 2 comes in first, this data is the leading pattern ld c Since it does not correspond to any bit of b a j, Z is outputted via FF and is given a state number 0, making the ROM contents 0υ.Therefore, the next data is waited in the form of 00 C1. When data a is input, status number 1 is added and the contents of the ROM are “1”.
0''' and waits for the next data in the form of 0010.

Each time a bee is input in sequence, a corresponding state number 2 or 3 is assigned to each bee, and the next data is awaited in the form of 0020.0030. When d is input to the last 4th bit, it means that the pattern rdcbaJ has been input, and since this 9th turn indicates the beginning in the serial data transmission format, the contents of the ROM are set to "01". At this time, the leading/9th tangent detection signal d is sent to the FF.
The data is output from the terminal P of the terminal P and the subsequent data processing begins.

Although the above explanation was made using ROM, if the entire pattern is written every time the system is started up, it can be written to RAM.
There is no problem in using .

(7) Effects of the Invention As described above, according to the present invention, a ROM is used instead of the conventional shift register as a storage memory for serial input data.
(Read ONLY Memory) can be used, so the length of the pattern detection device can be kept constant regardless of the length of the pattern that constitutes the data.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of the conventional turn detection method;
The figure is a block diagram of the apparatus for the setan detection method according to the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. ROM...Read-only memory, FF...Flitno flop, C...Clock input terminal, D-data input terminal, P...Pattern detection signal output terminal〇Patent applicant Fujitsu Limited Patent application agent Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate Patent Attorney Yukio Uchida Patent Attorney Akira Yamaguchi

Claims (1)

[Claims] In a method for detecting a pattern of each data in a serial data transmission format in which one data consists of n bits, a unique state number is assigned to each of the n bits, and a first
When the bit-th information is input, the system waits for all input information of the second bit while holding the state number corresponding to the first bit, and repeats the same operation up to the nl-th bit of manual information as needed. A pattern detection method characterized in that a predetermined pattern detection signal is sent out when the n-th bit of information is input manually.