JPS5758437A - Frame synchronization detecting circuit - Google Patents

Frame synchronization detecting circuit

Info

Publication number
JPS5758437A
JPS5758437A JP55133781A JP13378180A JPS5758437A JP S5758437 A JPS5758437 A JP S5758437A JP 55133781 A JP55133781 A JP 55133781A JP 13378180 A JP13378180 A JP 13378180A JP S5758437 A JPS5758437 A JP S5758437A
Authority
JP
Japan
Prior art keywords
result
frame
detection
block
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55133781A
Other languages
Japanese (ja)
Other versions
JPS6343939B2 (en
Inventor
Hirohisa Karibe
Takao Moriya
Koji Mizushima
Masao Yamazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55133781A priority Critical patent/JPS5758437A/en
Publication of JPS5758437A publication Critical patent/JPS5758437A/en
Publication of JPS6343939B2 publication Critical patent/JPS6343939B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To decrease the number of frame memories, by building the frame synchronization bit in multiple bits into a block, monitoring each block for synchronizing multipoint and coding the result of detection of each block up to now. CONSTITUTION:The output of a frame memory circuit A storing an input signal the intermediate result of detection is inputted to a decoder outputting the final and intermediate result of detection. That is, when both input data enter, devices 7, 8 output the input bit and the bit before 2 frames or one frame to (c), (d), (e). The signal coding the result detected at (c), (d), (e) is outputted from terminals (f), (g). The terminals (a), (b) input the result outputted from the (f), (g) to a circuit B after three-frame bits, and a terminal (h) outputs the result if synchronism is detected.
JP55133781A 1980-09-26 1980-09-26 Frame synchronization detecting circuit Granted JPS5758437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133781A JPS5758437A (en) 1980-09-26 1980-09-26 Frame synchronization detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133781A JPS5758437A (en) 1980-09-26 1980-09-26 Frame synchronization detecting circuit

Publications (2)

Publication Number Publication Date
JPS5758437A true JPS5758437A (en) 1982-04-08
JPS6343939B2 JPS6343939B2 (en) 1988-09-01

Family

ID=15112835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133781A Granted JPS5758437A (en) 1980-09-26 1980-09-26 Frame synchronization detecting circuit

Country Status (1)

Country Link
JP (1) JPS5758437A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934743A (en) * 1982-08-23 1984-02-25 Fujitsu Ltd Pattern detecting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5934743A (en) * 1982-08-23 1984-02-25 Fujitsu Ltd Pattern detecting system

Also Published As

Publication number Publication date
JPS6343939B2 (en) 1988-09-01

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