JPH07307731A - Detecting circuit for frame synchronization pattern - Google Patents

Abstract

PURPOSE:To provide a frame synchronization pattern detection circuit where the circuit scale is small and power consumption is low. CONSTITUTION:This circuit is provided with a memory 10 and an address counter 16 inputting serial signals including frame synchronization patterns and converting these serial signals into parallel signals and a pattern comparison part 12 comparing whether the parallel signal converted in these circuits are matched with the frame synchronization patterns or not. The circuit is composed of a decision circuit 14 inputting the comparison result as to whether the parallel signal is matched with the frame synchronization pattern or not from this circuit, holding this comparison result in the case of the comparison result to the effect that the signal is the frame synchronization pattern, resetting the held contents when the comparison result to the effect that the signal is not the frame synchronization pattern is inputted and performing the detection output of the matching of the frame synchronization patterns when the comparison result to the effect that the signal is the synchronization pattern is continuously inputted a prescribed number of times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame sync pattern detection circuit, and more particularly to a frame sync pattern detection circuit which is advantageously applied to a device having a primary group interface.

[0002]

2. Description of the Related Art For example, in the case of detecting a synchronization pattern of a serially input primary group multiframe, the circuit configuration becomes simple and the RA can be performed at low cost.
A circuit using a memory element such as M is used.

FIG. 3 is a block diagram showing a conventional technique of a frame synchronization pattern detection circuit in such a primary group interface, in which a detection circuit for detecting a synchronization pattern of 24 multiframes of the primary group is shown. ing. In the case of 24 multi-frames, the synchronization pattern of "001011" is sequentially inserted into the frame bit position every 4 frames (1 frame 193 bits). Also,
In order to detect the synchronization pattern of 24 multi-frames, it is necessary to detect the above pattern twice consecutively.

In this way, when a 6-bit synchronization pattern is detected twice in succession, it is possible to detect a synchronization pattern match / mismatch by performing pattern comparison of parallel data of 2 × 6 (= 12) bits. it can. Therefore, the frame synchronization pattern detection circuit has at least 11 bits each including 11 input ports and 11 output ports.
A memory of x772 (193x4) words is required.
Therefore, in FIG. 3, 1 input as a serial signal
An 8-bit memory (RAM or the like) 20A, 20B for converting the next group signal into a parallel signal, a 772-ary address counter 16, and a pattern comparison circuit 22 for detecting a synchronization pattern match / mismatch.

In FIG. 3, 11 bits × 772 (19
3 bit x 4) word memory is required, so 8 bit x 10
Two 24-word general RAMs are used. Here, 11 bits are used because the primary group signal input to the input port I1 of the memory 20A is the direct pattern comparison circuit 2
This is because it is also input to 2.

[0006]

However, in such a conventional technique, since 12 bits of the synchronization pattern are simultaneously monitored, a memory of 11 bits × 772 words or more is required. Therefore, as shown in FIG. 3, for example, two RAMs with 8 bit I / O are required,
There has been a problem that the circuit scale increases and the power consumption increases.

An object of the present invention is to solve the above drawbacks of the prior art and to provide a frame synchronization pattern detection circuit having a small circuit scale and low power consumption.

[0008]

In order to solve the above-mentioned problems, the present invention inputs a serial signal containing a frame synchronization pattern and converts the serial signal into a parallel signal, and serial / parallel conversion means. The comparison means for comparing whether or not the parallel signal converted by the parallel conversion means matches the frame synchronization pattern, and the comparison result for whether or not the parallel signal matches the frame synchronization pattern are input from the comparison means, and the comparison result is input to the frame. If it is a synchronization pattern, it is retained, and if the comparison result indicating that it is not a frame synchronization pattern is input, the retained content is reset, and the comparison result indicating that it is a frame synchronization pattern is input a prescribed number of times in succession. In this case, it has a determining means for detecting and outputting the frame synchronization pattern match.

[0009]

According to the present invention, the serial signal including the frame synchronization pattern is converted into the parallel signal by the serial / parallel conversion means and input to the comparison means. The comparison means compares whether or not the input parallel signal has a frame synchronization pattern, and outputs a "match signal" to the determination means if the parallel signal is a frame synchronization pattern and outputs a "mismatch signal" otherwise. When the "match signal" is input, the determination means holds it until the "mismatch signal" is input, and when the "match signal" is continuously input a predetermined number of times, the determination means performs the detection output of the frame synchronization pattern match.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a frame synchronization pattern detection circuit according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment in which the frame synchronization pattern detection circuit according to the present invention is applied to a circuit for detecting a synchronization pattern of a primary group of 24 multiframes. Also in the case of the present embodiment, the synchronization pattern of "001011" is inserted in the frame bit position in sequence for every four frames (one frame of 193 bits), and the frame synchronization pattern detection circuit detects this pattern twice consecutively. It is assumed that the synchronization pattern match detection output is performed.

In FIG. 1, a memory 10 such as a RAM and an address counter 16 constitute a serial / parallel converter for converting a primary group signal which is a serial signal into a parallel signal. The memory 10 is a 6-bit I / O (I1
To I6, O1 to O6), each output port O1 to O5 is connected to the pattern comparison unit 12 that performs comparison and detection of the synchronization pattern, and each output port O1 to O4 is input port I2. To I5, respectively.

By connecting the output port and the input port in this way and outputting the 772-ary address to the memory 10 by the address counter 16, the pattern comparison of the synchronization pattern "001011" inserted in sequence every four frames is performed. It can be detected by the unit 12. In the present embodiment, by considering the characteristics of the synchronization pattern, it is possible to detect a 6-bit pattern instead of 12-bit synchronization pattern, hold the result, and determine whether or not the synchronization pattern is detected twice consecutively. , 12 bits, the same processing as in the case of detecting the synchronization pattern at the same time is performed. In this embodiment, the detection result of the 6-bit synchronization pattern is held by the input port I6 and the output port O6 of the memory 12.

The pattern comparison unit 12 inputs the most significant bit (MSB) when parallel conversion is performed from the primary group signal, and inputs the bits less than that from the output ports O1 to O5 of the memory 10 to generate 6 bits. I am doing parallel data comparison. Since the memory 10 is connected as described above, the larger the output port number is, the lower bit is, and the bit input from the output port O5 is the least significant bit (LSB). The pattern comparison unit 12 inputs "1" in the case of a frame synchronization signal when the parallel-converted 6-bit bit string is input.
If it is not a frame synchronization signal, “0” is output to the determination circuit 14.

The pattern comparison section 12 also outputs nothing to the determination circuit 14 when the pattern input in the process of the first frame synchronization signal and the subsequent second frame synchronization signal is input. Specifically, since the primary group signal is a serial signal, the pattern comparison unit 12 outputs “0”.
After detecting the synchronization pattern of 01011 "(A) and before inputting the synchronization pattern of" 001011 "," 010110 "(B)," 101100 "
(C), "011001" (D), "110010"
The parallel data of (E) and "100101" (F) are actually input. Therefore, the pattern comparison unit 12 does not output anything when the parallel data of (B) to (F) is input.

The determination circuit 14 is a circuit for outputting the determination result of synchronization pattern match / mismatch based on the comparison result input from the pattern comparison unit 12, and is connected to the input port I6 of the memory 10 and at the same time as the output port O6. Connected with. . That is, when the determination circuit 12 receives the comparison result of “1” from the pattern comparison unit 12, the determination circuit 12 outputs “1” to the input port I6 of the memory 10 and the output port O.
Sbit "1" output from 6 is next input from timing. When the pattern comparison unit 12 inputs the comparison result of “0”, the determination circuit 12 outputs “0” to the input port I6 of the memory 10 and sets Sbit output from the output port O6 to “0”. . The determination circuit 14 is
When "1" is input from the pattern comparison unit 14 while the Sbit of "1" is input, the synchronous pattern matching detection output is performed. Further, the determination circuit 14 determines that the Sbit of “1” is
When inputting "0" from the pattern comparison unit 14.
When "" is input, "0" is output to the input port I6, and Sbit output from the output port O6 is reset to "0".

FIG. 2 is a flow chart showing the operation of the embodiment of FIG. 1, and the operation of this embodiment will be described with reference to these figures. In FIG. 2, reference symbol S indicates Sbit, and reference symbol P indicates a pattern input to the pattern comparison unit 12. In the initial state, Sbit is set to "0" (S
100). When Sbit = "0", "00101"
When a sync pattern of 1 "(A) is detected (S10
2), the pattern comparison unit 12 outputs "1" to the determination circuit 14.

When "1" is input from the pattern comparison section 12, the decision circuit 14 outputs "1" to the input port I6 of the memory 10 and sets Sbit to "1" (S10).
4). After that, the pattern comparison unit 12 displays “010110”.
(B), "101100" (C), "011001"
(D), "110010" (E), "100101"
When the parallel data of (F) is input (S106, S1
08), since the pattern comparison unit 12 does not output anything, S
The bit is held at "1" (S104).

The pattern comparison unit 12 is "100101".
When the synchronization pattern of "001011" (A) is detected after (F), "1" is output to the determination circuit 14 (S10).
6). When "1" is input from the pattern comparison unit 12 in the state where Sbit is "1", the determination circuit performs detection output of synchronization pattern matching (S110).

Although the present invention is applied to the detection of the synchronization pattern of the primary group frame in the present embodiment, the present invention is not particularly limited to this, and the synchronization pattern detection of the frame which requires simultaneous multipoint monitoring. It can be applied to circuits.

[0021]

As described above, according to the frame synchronization pattern detection circuit of the present invention, the number of storage elements can be reduced by half, so that the circuit scale can be reduced and the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame synchronization pattern detection circuit according to the present invention.

2 is an operation flow showing the operation of the embodiment of FIG.

FIG. 3 is a block diagram of a frame synchronization pattern detection circuit in the related art.

[Explanation of symbols]

 10 memory 12 pattern comparison unit 14 determination circuit 16 address counter

Claims (3)

[Claims] 1. A serial / parallel conversion means for inputting a serial signal including a frame synchronization pattern and converting the serial signal into a parallel signal, and a parallel signal converted by the serial / parallel conversion means is the frame synchronization pattern. The comparison means for comparing whether or not they match, and the comparison result of whether or not they match the frame synchronization pattern are input from the comparison means, and if the comparison result indicates that the frame synchronization pattern, this is input. If the comparison result indicating that the frame synchronization pattern is not held is input and the held content is reset, and the comparison result indicating that the frame synchronization pattern is input is input a predetermined number of times in succession, the frame synchronization pattern matches. A frame synchronization pattern detection circuit comprising: a determination unit that performs detection output. 2. The detection circuit according to claim 1, wherein the serial / parallel conversion means includes a plurality of input terminals and output terminals, and each output terminal for performing parallel conversion output is connected to an input side of the comparison means. And an n-th (n = 1, 2, 3, ...) Output terminal is connected to the (n + 1) -th input terminal, and an address signal is output to the storage element. A frame synchronization pattern detection circuit, comprising: an address counter that outputs the frame synchronization pattern inserted at regular intervals to the comparison means. 3. The detection circuit according to claim 2, wherein the comparing means includes a first frame sync signal and a second frame following the first frame sync signal.
The frame synchronization pattern detection circuit is characterized in that when the pattern input in the process of the frame synchronization signal is input, the comparison result is not output to the determination means.