JPH05219022A - Fault detection system - Google Patents

Abstract

PURPOSE:To confirm that N-M series conversion is correctly performed. CONSTITUTION:An input vertical parity arithmetic circuit 103 performs input vertical parity arithmetic, bit by bit (in every one-clock cycle), from N series input data signal series 1 and outputs an input vertical party signal 2. With an N-bit interval signal 6, an output horizontal parity arithmetic circuit 104 performs output horizontal parity arithmetic in every N-bit interval cycle for M output data signal series 5 and outputs M series of N-bit width output horizontal parity signals 7. For the M series of horizontal parity signals 7, an output vertical parity arithmetic circuit 105 performs output vertical parity arithmetic at intervals of the N-bit width parity signal and outputs an output vertical parity signal 8. A fault detecting circuit 106 compares the input vertical parity signal 2 with the output vertical parity signal 8. When the comparison result indicates a coincidence, it is judged that a series converting circuit 102 is normal, but when not, its fault is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection method, and more particularly to a failure detection method for column conversion in digital communication.

[0002]

2. Description of the Related Art Conventionally, in digital communication, column conversion failure detection has not been performed.

[0003]

Conventionally, since the failure of column conversion in digital communication has not been detected, it has not been possible to confirm the column conversion failure.

[0004]

In the fault detection system according to the present invention, a vertical parity operation is performed for each bit (every one clock cycle) from an input data signal N (N ≧ 2 integer) column to obtain an input vertical parity signal. And an input vertical parity operation circuit for outputting N columns to convert N columns to an integer (MM ≧ 1) column
M column conversion circuit and NM column converted output data signal M
A horizontal parity arithmetic circuit for performing horizontal parity arithmetic at N-bit intervals (every 1 clock cycle after N × M column conversion) for each column, and N-bit interval horizontal parity signal M columns (only when M ≧ 2 is an integer) Output vertical parity operation circuit that performs the vertical parity operation of the above and outputs the output horizontal / vertical parity signal, and the failure detection circuit that detects the failure by comparing the input vertical parity signal and the output horizontal / vertical parity signal, and the column conversion And a timing signal generation circuit for generating a timing signal required for the above.

[0005]

The present invention will now be described in more detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIGS. 1 and 2, in one embodiment of the present invention, an N-column (N ≧ 2 integer) input data signal sequence 1 is generated by a timing signal generation circuit 101 together with a frame signal 3. Column conversion timing signal 4
As a result, the N-M column conversion circuit 102 converts the data into M columns (an integer of M ≧ 1) and outputs the output data signal sequence 5.

For detection of a fault, the input vertical parity calculation circuit 103 performs an input vertical parity calculation for each bit (every one clock cycle) from the N columns of input data signal sequence 1 and outputs an input vertical parity signal 2. To do. Next, according to the N-bit interval signal 6 (1 bit is 1 clock cycle after column conversion) generated by the timing signal generation circuit 101, the output data signal sequence 5 of M columns is output by the output horizontal parity operation circuit 104. The output horizontal parity calculation is performed every N bit intervals, and the output horizontal parity signal 7 of M columns and having an N bit width is output. The output vertical parity arithmetic operation circuit 105 performs the output vertical parity arithmetic operation on the horizontal parity signal 7 of the M column for each parity signal of N-bit width, and outputs the output vertical parity signal 8. The fault detection circuit 106 compares the input vertical parity signal 2 with the output vertical parity signal 8. If the comparison results match, the column conversion circuit 102 determines that they are normal, and if they do not match, it determines that there is a failure and outputs the determination result output signal 9.

[0008]

As described above, according to the present invention,
An input vertical parity signal calculated from the N-column input signal sequence,
The output horizontal parity signal obtained by calculating the output data sequence after N-M consecutive conversion every M columns at N-bit intervals is compared with the result of the output vertical parity calculation, and the fault is detected. It can be confirmed that M column conversion has been performed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2 is a time chart of signals in the embodiment shown in FIG. 1. FIG.

[Explanation of symbols]

 1 input data signal sequence 2 input vertical parity signal 3 frame signal 4 column conversion timing signal 5 output data signal sequence 6 N bit interval signal 7 output horizontal parity signal 8 output vertical parity signal 9 judgment result output signal 101 timing signal generation circuit 102 columns Conversion circuit 103 Input vertical parity arithmetic circuit 104 Output horizontal parity arithmetic circuit 105 Output vertical parity arithmetic circuit 106 Fault detection circuit

Claims (1)

[Claims] 1. In a column conversion in a digital wireless communication system, vertical parity calculation is performed for each bit (every one clock cycle) from an input data signal N (N ≧ 2 integer) column, and an input vertical parity signal is output. An input vertical parity operation circuit, an N-M column conversion circuit for converting N columns into MM ≧ 1 columns, and an N-bit interval (N × N × N) for each M-column converted output data signal M columns. A horizontal parity calculation circuit for performing horizontal parity calculation at every clock cycle after M column conversion, and vertical parity calculation for N column interval horizontal parity signal M columns (only when M ≧ 2 is an integer) are performed to output horizontal A fault detection circuit that compares the input vertical parity signal and the output horizontal / vertical parity signal with the output vertical parity arithmetic circuit that outputs the vertical parity signal to detect a fault. If failure detection method characterized by having a timing signal generating circuit for generating a timing signal required for row conversion.