JPS6341937U - - Google Patents

Info

Publication number
JPS6341937U
JPS6341937U JP1986134852U JP13485286U JPS6341937U JP S6341937 U JPS6341937 U JP S6341937U JP 1986134852 U JP1986134852 U JP 1986134852U JP 13485286 U JP13485286 U JP 13485286U JP S6341937 U JPS6341937 U JP S6341937U
Authority
JP
Japan
Prior art keywords
circuit
converter
output
converts
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986134852U
Other languages
English (en)
Other versions
JPH066630Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986134852U priority Critical patent/JPH066630Y2/ja
Priority to US07/090,544 priority patent/US4808998A/en
Publication of JPS6341937U publication Critical patent/JPS6341937U/ja
Application granted granted Critical
Publication of JPH066630Y2 publication Critical patent/JPH066630Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】
第１図および第２図は、この考案の実施例を示
すもので、第１図は全体構成を示すブロツク図、
第２図は各構成の出力波形を示すもので、第２図
Ａは、同期回路がある場合を示し、第２図Ｂは同
期回路が無い場合を示すものである。第３図は従
来例を示す構成図である。 ２：Ｄ／Ａコンバータ、３：オペアンプ、４：
ビツト検出回路、５：同期回路、６：加減算回路
、ＶＲ１：可変抵抗器、１１：シリアルデータ入
力端、１２：データラツチ信号入力端、１３：ビ
ツトクロツク入力端。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) Ｄ／Ａコンバータにおいて、 入力データより任意のビツトの論理値を検出する
    ビツト検出回路と、このビツト検出回路の出力を
    Ｄ／Ａコンバータのアナログ出力と同期させる同
    期回路と、この同期回路より出力された出力電圧
    値を任意のレベルのＤＣ電圧に変換する加減算回
    路とを設け、前記加減算回路の出力を前記Ｄ／Ａ
    コンバータのアナログ出力に加算するように構成
    されていることを特徴とするＤ／Ａコンバータの
    歪低減回路。 (2) 加減算回路の入力レベル差を可変すること
    により、歪補正量調整を行なうように構成されて
    いることを特徴とする実用新案登録請求の範囲第
    １項記載のＤ／Ａコンバータの歪低減回路。
JP1986134852U 1986-09-04 1986-09-04 Ｄ／ａコンバ−タの歪低減回路 Expired - Lifetime JPH066630Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1986134852U JPH066630Y2 (ja) 1986-09-04 1986-09-04 Ｄ／ａコンバ−タの歪低減回路
US07/090,544 US4808998A (en) 1986-09-04 1987-08-28 Distortion reduction circuit for a D/A converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986134852U JPH066630Y2 (ja) 1986-09-04 1986-09-04 Ｄ／ａコンバ−タの歪低減回路

Publications (2)

Publication Number Publication Date
JPS6341937U true JPS6341937U (ja) 1988-03-19
JPH066630Y2 JPH066630Y2 (ja) 1994-02-16

Family

ID=15137976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986134852U Expired - Lifetime JPH066630Y2 (ja) 1986-09-04 1986-09-04 Ｄ／ａコンバ−タの歪低減回路

Country Status (2)

Country Link
US (1) US4808998A (ja)
JP (1) JPH066630Y2 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02128522A (ja) * 1988-11-09 1990-05-16 Nakamichi Corp デグリッチ回路
US5198814A (en) * 1990-11-28 1993-03-30 Nec Corporation Digital-to-analog converter with conversion error compensation
US5684481A (en) * 1994-03-18 1997-11-04 Analog Devices Rail-to-rail DAC drive circuit
USRE38083E1 (en) * 1994-03-18 2003-04-22 Analog Devices, Inc. Rail-to-rail DAC drive circuit
GB2299228B (en) * 1995-03-13 1998-08-05 Yamamura Churchill Limited A digital to analogue converter
JP4416254B2 (ja) * 2000-02-24 2010-02-17 キヤノン株式会社 画像形成装置
US6937178B1 (en) 2003-05-15 2005-08-30 Linear Technology Corporation Gradient insensitive split-core digital to analog converter
US8981982B2 (en) * 2013-04-05 2015-03-17 Maxlinear, Inc. Multi-zone data converters

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232657A (en) * 1975-09-09 1977-03-12 Fujitsu Ltd Digital-analog converter
JPS57104320A (en) * 1980-12-22 1982-06-29 Nec Corp Digital-analogue converter

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5337365A (en) * 1976-09-18 1978-04-06 Nippon Telegr & Teleph Corp <Ntt> Correcting method of d/a converting error for d/a converter
JPS5953727B2 (ja) * 1977-04-06 1984-12-26 株式会社日立製作所 補正回路付ｄａ変換器
US4342983A (en) * 1980-08-11 1982-08-03 Westinghouse Electric Corp. Dynamically calibrated successive ranging A/D conversion system and D/A converter for use therein
US4323885A (en) * 1980-09-29 1982-04-06 Bell Telephone Laboratories, Incorporated Noise and crosstalk reduction in mid-riser biased encoders

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232657A (en) * 1975-09-09 1977-03-12 Fujitsu Ltd Digital-analog converter
JPS57104320A (en) * 1980-12-22 1982-06-29 Nec Corp Digital-analogue converter

Also Published As

Publication number Publication date
US4808998A (en) 1989-02-28
JPH066630Y2 (ja) 1994-02-16

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