JPS6341094B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormality detection circuit for detecting abnormalities such as temporary malfunctions caused by noise or the like in electronic computers, particularly small-sized electronic computers.

FIG. 1 shows an example of a conventional abnormality detection circuit. This circuit is generally called a watchdog timer. Its configuration and operation will be explained with reference to FIG.

A program stored in a small computer includes an instruction to output a clear signal CL to the output port 11 every program execution cycle. This clear signal CL is input to the counter 13 and is cleared at every fixed period _T0 . On the other hand, the counter 13 stores the one-round time in advance.
A count value K ₀ corresponding to a time greater than T ₀ is preset. Therefore, under normal conditions, the counter receives the reference clock signal CK from the oscillator 12.
is counted and cleared by the clear signal CL that is input every fixed period _T0 . This means that the program is being executed normally.

However, if the program goes out of control or stops for some reason, the clear signal CL will not be output from the output port 11. Then, the counter 13 continues counting and its count value increases. When the count value reaches the preset count value _K0 , the counter 13 outputs a set signal SET, and this set signal SET is R
-Set flip-flop 14. The flip-flop 14 maintains this state, and
At the same time as the Q output is set, an abnormal signal WDT is generated from the Q output.
Output.

The abnormality signal WDT is output regardless of any abnormality in the software or hardware of the computer, and causes the operation of the computer and its peripheral devices to stop.

Possible causes of such an abnormality are as follows.

(i) Cases caused purely by hardware failures (ii) Cases caused by program errors under special conditions in the software known as bugs (iii) Cases caused by malfunctions due to noise Regarding (i) above, there has been a recent Due to advances in semiconductor technology, the failure rate can be said to be almost negligible. (ii)
Because the program is debugged before it is implemented, this phenomenon only occurs under very specific conditions, and it is extremely unlikely to occur again even after restarting. Regarding (iii), it is a simple malfunction and there is no problem in restarting it, but especially when used as industrial equipment, it is often used in environments where noise is likely to occur, so the frequency of occurrence of malfunction itself is low. Relatively expensive.

Among the above causes, (i) is fatal because it is a failure of the hardware itself, but cases (ii) and (iii) are software problems, so once the cause is confirmed, it can be remedied. Activation is possible.

In this case, conventionally, when the control device is stopped due to the operation of the abnormality detection circuit, an operator or the like confirms the failure and then resets the flip-flop 14 using the initial reset signal INT to restart the control device. However, such work is complicated and requires a lot of recovery time.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an abnormality detection circuit that enables automatic and easy restart using CPU interrupt processing.

The present invention will be described in detail below based on illustrated embodiments. FIG. 3 shows an embodiment of the abnormality detection circuit according to the present invention. Note that the same parts as in FIGS. 1 and 2 are given the same reference numerals, and the details are the same, so the explanation will be omitted.

The parts that differ from Figure 1 are the output port 15 that outputs the reset signal RS, the reset signal RS, and the manual initial reset signal INT when the power is turned on again.
The reset signal is input to flip-flop 1.
4 is provided with an OR circuit 16 that outputs an output to 4. Although not shown, the abnormality signal WDT is given to the CPU as an interrupt signal in addition to the safety circuit of the control device, and as will be described later, the CPU sends it to the output port 15 after checking for abnormal conditions. A reset signal output command is given.

In Figure 3, the abnormality detection operation itself is the first
This is the same as the case shown in the figure. That is, counter 13
The count value reaches _K0 , and the flip-flop 14 outputs an abnormal signal WDT.

The abnormal signal WDT is input to the CPU interrupt input,
The CPU starts the interrupt processing described below. Fourth
The figure is a flowchart of CPU interrupt processing.
When the abnormality detection signal WDT is input to the CPU as an interrupt request signal, the CPU first prohibits all interrupts. At this time, although the control device has already stopped operating due to the abnormal signal WDT, the CPU executes a command to change the output state to a safer state. Next, check how many times this abnormal state has occurred. In this embodiment, only one restart is permitted, and therefore, if the abnormal state occurs for the second time, the system will be in a stopped state. On the other hand, a checksum of the main program is executed only when the abnormal state occurs for the first time. Here, checksum means to treat all programs as numbers, add them from the beginning to the end, and compare that value with a pre-given total addition value. Therefore, in the checksum, it is checked whether the program at the time of writing has changed since then. As a result of the checksum, if the total addition value of the number of programs does not match, it means that the program has been destroyed and is stopped. If correct, the CPU outputs a clear signal CL from the output port 11 and outputs a reset signal RS from the output port 15.

As a result, the counter 13 is cleared and the flip-flop 14 is reset. At this time, if there is no failure in the memory, CPU, or bus line (not shown), the flip-flop 14 will be reset.

Next, among the previously prohibited interrupt processes, only the interrupt input related to the abnormal signal WDT is permitted.
If the previous reset operation of the abnormal signal WDT has failed, the abnormal signal WDT remains output, so this interrupt processing is repeated again, and as a result, the abnormal state occurs for the second time, so the system is stopped. , safety is ensured.

If the abnormal signal WDT has been reset, the program jumps to the beginning of the main program and starts executing instructions from the initial state.

Now, when the abnormality signal WDT is reset, the computer becomes ready for operation, and the computer starts up again and starts operation.

As mentioned above, even if an abnormality is detected once and the abnormality detection signal WDT is output and the operation of the control device is stopped, a signal based on the result of determining whether restarting is possible due to CPU interrupt processing will cause a fatal failure. Otherwise, it will be automatically stopped or restarted. It becomes possible to quickly respond to malfunctions caused by noise or software errors, which account for a large proportion of failures.

[Brief explanation of the drawing]

FIG. 1 is a conventional abnormality detection circuit, FIG. 2 is an operation timing chart thereof, FIG. 3 is a circuit diagram showing an embodiment of the abnormality detection circuit according to the present invention, and FIG. 4 is a flowchart of interrupt processing. 11... Output port, 12... Oscillator, 13... Counter, 14... Flip-flop, 16... OR circuit, CL... Clear signal, CK... Clock signal,
WDT...Abnormality detection signal, SET...Set signal, RS
...Reset signal, INT...Initial reset signal.

Claims (1)

[Claims] 1 For each program execution cycle
a first output port that outputs a clear signal in response to a command from the CPU; a counter that is cleared by the clear signal and outputs a set signal when it counts a count value greater than the one cycle time; An abnormality detection circuit for an electronic computer, comprising: an oscillator that outputs a clock signal; and a flip-flop that receives and holds the set signal and outputs an abnormality detection signal for stopping execution of the program. a second output port that inspects the contents of the program when an abnormality detection signal is output and outputs a reset signal if there is no error; and an initial reset signal that indicates when the power is turned on. An anomaly detection circuit for a computer, comprising: an OR circuit that resets the flip-flop in order to restart the program when any of the above is given. 2. An abnormality detection circuit for a computer according to claim 1, wherein the content of the program is checked by checking a checksum of a digital data string constituting the program. 3. The computer according to claim 1 or 2, wherein the second output port is configured not to output the reset signal when the abnormality detection signal is abnormally output a predetermined number of times. abnormality detection circuit.