JPH01166145A - Cpu monitor - Google Patents

Abstract

PURPOSE:To surely execute monitoring processing of both hardware and software by executing interlockingly an interruption inhibiting processing precedent to the execution of an action monitoring program and the clear processing of a watchdog timer. CONSTITUTION:An interruption inhibiting instruction precedent to the execution of the action monitoring program is executed and a CPU 1 gets into an interruption inhibiting condition. At the same time, an address is sent onto an address bus and thus, an address coincidence detecting circuit 10 detects this. A condition coincidence detecting circuit 11 detects that an execution action is executed in the CPU 1. When the CPU 1 is normal, a trigger is applied to a retriggerable monostable multivibrator 6 to constitute the watchdog timer. When the CPU 1 is abnormal, the above-mentioned trigger is not applied and a reset is applied. When the interruption inhibiting instruction is executed and the interruption inhibiting processing is executed, a clear is applied to the watchdog timer and the action of the action monitoring program is guaranteed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention provides hardware monitoring processing using a watch dog timer and software monitoring processing using an operation monitoring program. A CPU designed to be used in conjunction with
Regarding monitoring equipment.

(Prior Art) Conventionally, in this type of CPU monitoring device, as shown in FIG. 7, an address/number configuration circuit 2 is provided for each of the address bus, data bus, and control signal line. By connecting the data coincidence detection circuit 3 and the state coincidence circuit 4 and guiding their outputs to the AND gate 5, it is possible to detect that the CPU 1 has executed an instruction to write specific data to a specific address, and to The detection output triggers a retriggerable monomulti 6 that functions as a watch dog timer, and the output of the retriggerable monomulti 6 is used as a reset signal to reset the CPU.

On the other hand, in the system memory included in the other circuit 7, a CPU monitoring program is stored as a subroutine, as shown in the flowchart of FIG. 8 and the program list of FIG.

In this subroutine program, as shown in Fig. 8, the interrupt status is first saved (step 801), and then an interrupt disable instruction is executed to disable external interrupts (step 802). Write specific data and clear the watch dog timer (step 803).

After that, the operating state is monitored by software (step 804), and if the operation is abnormal, it is stopped (step 805),
After the abnormality processing is performed (step 806), the interrupt state recovery processing is executed (step 807), and the process returns to the previous routine.

In this way, in this conventional device, as shown in FIG.
By writing this and periodically executing it, you can monitor the operation of the CPU using hardware, and at the same time
The operation monitoring program shown in the figure (steps 804 to 8
By executing 06), the operation of the CPU is also monitored from a software perspective.

(Problem to be Solved by the Invention) However, in such conventional CPU monitoring devices, if an instruction to output specific data to a specific address is written in the system program, the The watch dog timer was configured to be cleared immediately, so if a similar description existed elsewhere in the system due to a programming error, the C
There may be cases where CPtJl cannot be reset even though the PU is out of control.

Furthermore, as shown in FIG. 9, since the interrupt disable instruction 9 and the timer clear instruction 8 are separate instructions, if the timer clear instruction 8 is structured and made into a subroutine, CPIJl may run out of control. As a result, only the timer clear instruction 8 is executed without passing through the interrupt disable instruction 9, and since in this state interrupts are enabled, another interrupt occurs immediately after the execution of the timer clear instruction 8, causing software-like operation. If the abnormality monitoring processing (steps 804 to 806) is skipped, an abnormality in the operation of the CPU 1 will occur regardless of whether the above-mentioned hardware processing by the watch dog timer or the above-mentioned software operation monitoring processing is performed. The problem is that it is not possible to check.

An object of the present invention is to provide a CPU monitoring device of this type that uses both hardware processing and software processing to prevent programming errors.

The object of the present invention is to ensure that both the hardware-based abnormality monitoring processing and the software-based abnormality monitoring processing described above are executed regardless of the runaway of the CPU or the like.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an operation monitoring system that is stored in the system memory and has a small number of interrupt disabling instructions at the beginning of the system memory. A watch that is assigned to the same address as the storage address of the interrupt disabling instruction, that is cleared when the CPU executes an execution operation with that address specified, and that resets the CPU using the time-up signal. - It is characterized by being equipped with a dog timer, and configured so that interrupt disabling processing prior to execution of the operation monitoring program and clearing processing of the watch dog timer can be performed simultaneously in conjunction with each other.

(Operation) According to such a configuration, the watch dog timer is not cleared unless an instruction written at a specific address in the system program memory is executed.

Therefore, the watch dog due to blockraming mistakes
Erroneous clearing of the timer can be reliably prevented.

Furthermore, at the time the watch dog timer is cleared, the interrupt is always disabled, so there is no possibility that another interrupt will occur and the operation monitoring program will be skipped.

(Embodiment) Fig. 1 is a block diagram showing the hardware configuration of an embodiment of the CPU monitoring device according to the present invention, Fig. 2 is a flowchart showing the software configuration thereof, and Fig. 3 is the main part of the operation monitoring program. This is a program list showing.

In these figures, the same components as those in the conventional example are designated by the same reference numerals, and the explanation thereof will be omitted.

In FIG. 1, an address/number output circuit 10 detects that a specific address (1237) is output on the address bus, and a state/number output circuit 11 detects that a control signal indicates an execution state. It is designed to detect the presence of water.

The outputs of these circuits 10 and 11 are applied to the retriggerable monomulti 6 via an AND gate 12.

In other words, from a hardware perspective, the retriggerable monomulti 6 that constitutes the watch dog timer is triggered when the CPU performs an execution operation while the address (1237>) is being output on the address bus. It is made to be done.

FIG. 4 is a circuit diagram representing the block diagram shown in FIG. 1 using more specific elements.

In this figure, an MPU 8085 is used as the CPU 1, and an address/number configuration circuit 10. State coincidence detection circuit 1
1 and AND gate 12, each address bit,
The control bits are appropriately inverted using an inverter.

In addition, as a retriggerable mono multi 6, an external resistor R
A retriggerable monomulti circuit element using nine external capacitors C is used.

On the other hand, as shown in FIG. 3, an interrupt disable instruction 9 (DI
> is stored, and a software operation monitoring program (steps 203 to 206) is written at the address following it, as shown in FIG.

Next, the operation of the apparatus of this embodiment having the above configuration will be explained with reference to the time chart of FIG. 5 and the CPtJ status table of FIG. 6.

When the CPU is operating normally, the subroutine program shown in FIG. 2 is executed periodically.

That is, in the first step, addresses (1234), (1235), (12
36) by sequentially executing the instructions stored in
The interrupt state is saved (step 201).

Next, the vJ inclusion prohibition instruction 9 (DI) stored at address (1237) is executed, and the CPU
1 indicates that interrupts are disabled.

At the same time, as shown in FIG. 1, an address (1237) is sent onto the address bus, which is detected by the address-number configuration circuit 10, and is also sent on the control signal line as shown in FIG. signal S so that
o=1. When S+=1, the state-number construction circuit 11 detects that an execution operation has been performed in the CPU 1.

As a result, the retriggerable monomulti 6 constituting the watch dog timer is triggered.

Therefore, as shown in FIG. 5, when CPU i is normal, the external capacitor C is repeatedly discharged at each point of P+, R2, R3, and R4, and the output G3 of the monomulti 6 is is maintained at L'', and the CPU is not reset.

On the other hand, if the CPU 1 goes out of control and stops executing the subroutine program shown in FIG. As t1 progresses, the output G3 of the monomulti 6 changes from II L 11 to “H”.
The process shifts to II, and as a result, the CPU 1 is reset.

In addition, in the case of this embodiment device, in order to trigger the retriggerable monomulti 6 that constitutes the watch dog timer, there is no choice but to write some kind of command at the address (1237). Furthermore, occurrence of timer clear processing due to programming errors etc. can be reliably prevented.

Further, when an interrupt disabling instruction is executed and interrupt disabling processing is performed, the watch dog timer is simultaneously cleared in conjunction with this. Moreover, the interrupt prohibition command is
Since it is written at the beginning of the operation monitoring program (steps 203 to 205), if the interrupt disable instruction is executed,
Thereafter, even if an interrupt signal arrives, the operation monitoring program (steps 203 to 205) is guaranteed to be executed, and unlike the conventional device, these programs are never skipped.

Therefore, according to this embodiment, the watch dog
Both hardware-based CPU monitoring using a timer and software-based CPU monitoring using an operation monitoring program (steps 203 to 205) can be performed reliably in any case.

[Effects of the Invention] As is clear from the above description of the embodiments, according to the present invention, a CPU that uses this type of hardware-based CPU monitoring processing and software-based CPU monitoring processing in combination.
In the PU monitoring device, both processes can be performed reliably in any case, and the reliability of this type of device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the hardware configuration of an embodiment of the device of the present invention, FIG. 2 is a flowchart showing the software configuration, FIG. 3 is a program list showing main parts of the operation monitoring program, and FIG. Figure 4 is a circuit diagram showing a more specific circuit configuration of the same device, Figure 5 is a time chart showing the operation, Figure 6 is a state diagram showing the state of the control signal line, and Figure 7 is the hardware of the conventional device. This is a program list that accepts the software configuration. 1... CPU 6... Retriggerable monomulti 9... Interrupt disable instruction 10... Address match detection circuit 11... State match detection circuit 12... AND gate

Claims (1)

[Claims] (1) An operation monitoring program that is stored in the system memory and has at least an interrupt disabling instruction at the beginning thereof, and a state in which the program is assigned to the same address as the storage address of the interrupt disabling instruction, and that address is specified. The watchdog timer is cleared when the CPU performs an execution operation, and is further reset by the time-up signal. A CPU monitoring device characterized in that the CPU monitoring device is configured such that the clearing process can be performed at the same time in conjunction with the clearing process.