JP2001242901A - Device for detecting malfunction of programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for detecting malfunction of programmable control ler which can restart automatically after a temporary suspension of system operation even if malfunction of a memory occurs. SOLUTION: A circuit 13 for detecting malfunction of the memory outputs signal 15 for detecting malfunction of the memory to an NMI detection circuit 17 and a timer circuit 23 respectively when the malfunction of the memory is detected. The NMI detection circuit 17 which inputs the signal 15 for detecting malfunction of the memory outputs an NMI signal 19 to a CPU 21 which suspends after executing processing of the NMI, while the timer circuit 23 which inputs the signal 15 for detecting malfunction of the memory starts timer operation and outputs a reset signal 25 reacting to malfunction of the memory in a reset circuit 27 when data of the timer reaches a fixed value. The reset circuit 27 outputs a system reset signal 29 to the suspending CPU 21 to restart it after the temporary suspension.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller abnormality detecting device capable of automatically restarting even when a memory abnormality occurs.

[0002]

2. Description of the Related Art Generally, a microprocessor (CPU) is used as an operation / control device of a programmable controller, and a ROM and an R / D are used as data storage devices.
AM is used. The RAM is a readable and writable memory, is used as a work area of the microprocessor, and is used for storing user programs and control data.

Conventionally, as shown in FIG. 5, an abnormality detection device 111 of a programmable controller uses a parity check or an ECC (Error Checking and Correction) to check the validity of data stored in a RAM.
) Checks were used.

[0004] Such an abnormality in the parity or the ECC means a data destruction or loss of the whole or a part of the RAM, and thus is a fatal abnormality in the operation of the programmable controller.

Therefore, the memory unit 113 and the data bus 1
The memory abnormality detection circuit 117 connected via the memory 15 detects the occurrence of an abnormality on the memory unit 113 or the data bus 115 and detects a memory abnormality detection signal 11
9 to the NMI detection circuit 121 and the NMI detection circuit 1
21 notifies the CPU 129 of the NMI signal 123 to stop the operation of the system.

Here, if the cause of the abnormality is a permanent (continuous) problem due to a memory element failure or the like, after the system is stopped, the cause is removed by replacing the memory card or the like, and the system is restored. Was.

[0007]

However, many of the causes of parity errors and ECC errors are transient transient problems in which a part of data is destroyed or lost due to noise or the like. In most cases, simply restarting the system after stopping it would recover the system.

In this case, for example, it is necessary to reset the CPU 129 by artificially operating a reset button or the like provided in the reset circuit 125 to reset the CPU 129 and restart the system.

[0009] The present invention has been made in view of the above,
An object of the present invention is to provide a programmable controller abnormality detection device that can automatically stop and then automatically restart a system operation even when a memory abnormality occurs.

[0010]

According to the first aspect of the present invention,
In order to solve the above-described problem, in a programmable controller abnormality detection device that stops the operation of a programmable controller when an abnormality occurrence in a memory for storing data or a data bus is detected, the occurrence of the abnormality is detected, and The gist of the present invention is to include a reset unit that generates a reset signal for restarting the programmable controller after the operation is temporarily stopped.

According to a second aspect of the present invention, in order to solve the above problem, the reset means determines whether or not to generate the reset signal according to a prohibition condition or a permission condition.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram showing a system configuration of an abnormality detection device for a programmable controller according to a first embodiment of the present invention.

First, the configuration of the abnormality detecting device 11 of the programmable controller shown in FIG. 1 will be described.

The memory abnormality detection circuit 13 is connected to the data bus 1
2 and connected to the memory unit 14 via a known parity check or ECC check to check the validity of the data read from the memory unit 14 and detect a memory abnormality such as data destruction or loss. in case of,
The memory abnormality detection signal 15 is output to the NMI detection circuit 17 and the timer circuit 23.

When the memory abnormality detection signal 15 is input from the memory abnormality detection circuit 13, the NMI detection circuit 17
The NMI signal 19 for stopping the operation of the PU 21 is
Output to PU21.

The timer circuit 23 outputs the memory abnormality detection signal 1
When 5 is input, the timer operation is started. When the timer data reaches a preset value, a memory abnormality interlock reset signal 25 is output to the reset circuit 27.

The reset circuit 27 outputs a system reset signal 29 for restarting the CPU 21 to the CPU 21 when the memory abnormality interlock reset signal 25 is input from the timer circuit 23.

The CPU 21 performs an NMI process in response to the input of the NMI signal 19, and enters an operation stop state after completing the NMI process. In addition, the CPU in the operation stopped state
21 is restarted in response to the input of the system reset signal 29.

Next, the operation of the abnormality detecting device 11 for the programmable controller according to the first embodiment will be described with reference to the timing chart shown in FIG.

A memory abnormality detection circuit 13 connected to the memory unit 14 via the data bus 12 performs a known parity check or ECC check, and when a memory abnormality such as data destruction or loss is detected, a memory abnormality detection signal is output. 15 (t1) is output to the NMI detection circuit 17 and the timer circuit 23.

When the memory abnormality detection signal 15 (t1) is input from the memory abnormality detection circuit 13, the NMI detection circuit 17 outputs an NMI signal 19 (t2) to the CPU 21. Here, the CPU 21 executes the NMI process in response to the input of the NMI signal 19 (t2), stops the CPU operation after completing the NMI process (t3), and enters the operation stop state.

On the other hand, when the memory abnormality detection signal 15 (t1) is input, the timer circuit 23 starts a timekeeping operation, and resets the memory abnormality interlocking reset signal 25 (t4) when the timekeeping data reaches a preset value. Output to the circuit 27. Here, the timer set time (t4-t1) is C
It is set to be sufficiently longer than the NMI processing time (t3-t2) in the PU 21.

Finally, in the reset circuit 27 to which the memory abnormality interlock reset signal 25 (t4) is input from the timer circuit 23, the system reset signal 2 is sent to the CPU 21.
9 (t5) is output. As a result, the CPU 21 in the operation stopped state is restarted when the reset signal 29 (t5) ends (t6).

As a result, after a memory error occurs, the CPU
Temporarily shifts to the operation stop state, and is restarted in response to the system reset signal, so that the system can be automatically restarted without any manual operation.

(Second Embodiment) FIG. 3 is a diagram showing a system configuration of an abnormality detecting device 31 of a programmable controller according to a second embodiment of the present invention. In addition,
The second embodiment has the same basic configuration as the system configuration corresponding to the first embodiment shown in FIG.
The same components are denoted by the same reference numerals, and description thereof will be omitted.

The feature of the second embodiment is that the timer circuit 2
3 is a configuration in which an interlocking reset control signal 33 for controlling whether the output of the memory abnormality interlocking reset signal 25 to the reset circuit 27 is permitted or prohibited is added as an operation condition.

Next, the characteristic operation of the abnormality detecting device 31 of the programmable controller according to the second embodiment will be described with reference to the timing chart shown in FIG.

When the interlock reset control signal 33 is in the output permission state (0: permission), the operation is the same as in the first embodiment. On the other hand, when the interlock reset control signal 31 is in the output inhibited state (1: inhibited), even if the memory abnormality detection circuit 13 detects a memory abnormality, the timer circuit 23
Since the timekeeping operation does not start internally, the memory abnormality interlock reset signal 25 is not output to the reset circuit 27. Therefore, the operation stop state of the CPU 21 is maintained after the NMI processing is completed.

The output terminal of the memory abnormality interlock reset signal 25 generated by the timer circuit 23 is input to one input terminal of the gate circuit, and the other input terminal is used for interlock reset control for controlling output permission / inhibition. The signal 33 may be inputted, and whether or not the memory abnormality interlock reset signal 25 is output to the reset circuit 27 may be controlled according to the state of the interlock reset control signal 33.

As a result, even in the event of a permanent failure to stop the operation of the system due to the state of the interlocking reset control signal, it is possible to break the repetitive loop of system stop and system restart.

[0032]

According to the first aspect of the present invention, even in the case of a transient memory error which has conventionally had to stop the operation of the system, the system is automatically restarted without any manual operation. Be able to start.

According to the second aspect of the present invention, in addition to the effects of the first aspect, when a permanent failure to stop the operation of the system occurs, the system is stopped and the system is restarted. The operation of the system can be normally stopped without repeating the loop.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of an abnormality detection device for a programmable controller according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the abnormality detection device for the programmable controller according to the first embodiment.

FIG. 3 is a diagram illustrating a system configuration of an abnormality detection device for a programmable controller according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the abnormality detection device for a programmable controller according to the second embodiment.

FIG. 5 is a diagram showing a conventional abnormality detection device for a programmable controller.

[Explanation of symbols]

11, 31 Programmable controller abnormality detection device 12 Data bus 13 Memory abnormality detection circuit 14 Memory unit 15 Memory abnormality detection signal 17 NMI detection circuit 19 NMI signal 21 CPU 23 Timer circuit 25 Memory abnormality interlocking reset signal 27 Reset circuit 29 System reset signal 33 Interlock reset control signal

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Claims (2)

[Claims] An apparatus for detecting an abnormality of a programmable controller which stops an operation of a programmable controller when an abnormality on a memory or a data bus for storing data is detected, wherein the operation of the programmable controller is detected when the abnormality is detected. An abnormality detection device for a programmable controller, comprising: reset means for generating a reset signal for restarting the programmable controller after being temporarily stopped. 2. The abnormality detecting device for a programmable controller according to claim 1, wherein said reset means determines whether or not to generate said reset signal according to a prohibition condition or a permission condition.