JP2003050712A - Microcomputer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely execute a fault restoration processing, even when a fault occurs in an external bus in a microcomputer system. SOLUTION: A CPU 11, a built-in ROM 12 in which a fault restoration processing program is stored and a built-in RAM are positioned and connected internally via an internal bus 18 in a microcomputer device 1 connected with groups 5 to 8 of external equipment, an external ROM 3 and an external RAM 4 via an external bus 19, when an abnormality is detected by an abnormality detection processing part 2 and an interrupt request signal 21 is outputted, a storage area required for execution of the fault restoration processing program is set in the built-in RAM 13 and a fault restoration processing program in the built-in ROM 12 is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system using a microcomputer, and more particularly to processing when a system abnormality is detected.

[0002]

2. Description of the Related Art Conventionally, a failure recovery program corresponding to system abnormality processing has been stored in any of the memory spaces existing in the system without any special consideration. Further, the same applies to the arrangement of the control parameters to be referred to and rewritten in the execution process of the fault recovery program and the RAM as the storage destination of the program stack.

Alternatively, a method has been adopted in which the microcomputer is reset by an abnormality detection signal and the system is restarted in the same manner as when the power was turned on.

[0004]

However, with the above-described fault recovery program and the configuration in which the parameter data used by the program is read into the microcomputer via the external bus, the cause of the system fault is the address bus of the external bus or When it is on the data bus or the bus control signal line for reading and writing timing, there is a problem that the fault recovery program itself cannot be executed normally.

Further, if the system is abnormal due to a transient disturbance or the like, it can be normally restored by simply resetting the CPU. However, if the system is abnormal due to a fatal failure such as damage to an electronic circuit, the failure recovery program itself is used. There is a problem that an interrupt occurs due to abnormality detection repeatedly in a short time before completion, and the system is initialized each time.

In particular, a plurality of Cs in a master-slave configuration.
In the system that controls the mechanical mechanism by the PU, the initialization operation drives the mechanical mechanism, which causes the user to feel uneasy as if the device is moving unnaturally. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a microcomputer system capable of reliably executing a failure recovery processing program when an abnormality is detected.

[0008]

According to the present invention, as one means for achieving the above-mentioned object, the microcomputer system is provided with means.

According to another aspect of the present invention, a method for controlling a microcomputer system includes steps.

According to another aspect of the present invention, a storage medium stores a processing program for causing a computer to execute the steps.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram when applied to a facsimile apparatus as an embodiment of the present invention.

Since the facsimile machine is a machine of a nature that the operator does not intervene in the automatic receiving operation and must operate all night, reliability is very important and the invention is particularly effective.

Reference numeral 1 denotes a microcomputer device provided with the following 11 to 17 on one semiconductor chip.

Reference numeral 11 denotes a CPU which performs logical operation processing and controls the facsimile apparatus of this embodiment. Reference numeral 12 denotes a built-in ROM, which is a read-only memory that stores program codes executed by the CPU 11, data to be referred to, and the like. Reference numeral 13 is a built-in RAM that can be read and written by the CPU 11.

When the input / output terminal of the microcomputer device 1 is used as a general-purpose port, a port controller 14 controls the port function of the microcomputer device 1.
Operated by.

Reference numeral 15 denotes an external bus control unit which controls the expansion of the internal bus of the microcomputer device 1 to the outside of the device, and is operated by the CPU 11.

Reference numeral 16 denotes a built-in peripheral function unit built in the microcomputer device 1 having general-purpose functions such as a general-purpose timer, a counter, and interrupt control.

A port 17 of the microcomputer device 1 is programmable and the port controller 1 is programmable.
4, the external bus control unit 15, the built-in peripheral function unit 16
It is a terminal function control unit that selects and controls which of the signals to be connected to.

Next, reference numeral 2 is an abnormality detecting section, which constantly monitors the operating state of the present system and, when it judges that there is an abnormality, generates a non-maskable interrupt request to the microcomputer 1 by the interrupt request signal 21. As the abnormality detected by the abnormality detecting unit 2, generally, a watchdog timer times out, an access operation to a space where a device is not mapped, an R
Events such as execution of write access operations to the OM space can be cited.

The following 3 to 8 are to be accessed by the CPU 11 via the external bus 19.

Reference numeral 3 denotes an external ROM in which programs and data are fixedly written. An external RAM 4 stores control parameters, image data, and the like.

A reading unit 5 has a light source, conveys a document, converts an image into an electrical signal, and takes in the image. A recording unit 6 records the received image data on a sheet. A communication unit 7 is connected to a communication line and transmits / receives image data by a facsimile signal. Reference numeral 8 denotes an operation unit for inputting operation instructions to the apparatus and displaying operation states.

An internal bus 18 is connected to the above-mentioned 11 to 16 inside the microcomputer 1. 19 is
The internal bus 18 is an external bus that extends outside the microcomputer 1. A terminal group 20 functions as a general-purpose input / output port.

Reference numeral 21 denotes an interrupt request signal, which requests the CPU 11 to perform an interrupt process when the abnormality detector 2 detects an abnormality. Generally, non-maskable interrupts (NMI) are used for such applications.

Reference numeral 22 denotes one of the general-purpose input / output ports,
It is a reset signal defined as an initialization output signal of the system. A control signal group 23 is logically connected to the built-in peripheral function section 16.

The basic operation will be described below.

First, when power supply to the system is started, the microcomputer 1 starts operating in a predetermined default state. In this default state, only the internal bus 18 can be used, and the terminal function of the microcomputer 1 behaves as a general-purpose port. The program starts fetching from the internal ROM 12. According to this command, the setting of each built-in unit is changed from the default state to a desired state. As a result, the external bus 19 can be used.

After that, various processing units connected to the external bus 19 are initialized. A slave CPU is incorporated in each of the reading unit 5, the recording unit 6, the communication unit 7, and the operation unit 8, and it is also confirmed whether or not those operations can be normally started.

In this initialization, the light source is once turned on in the reading section 5 to adjust the light amount and the original position of the original conveying system is executed, and the recording section 6 confirms the operation of the sheet conveying system and the recording image forming process. Initialization drive of the mechanical mechanism part such as executed is executed.

After that, the standby state is entered, and the operation unit 8
An external R is issued by an operation instruction from the line or an incoming call from the line.
The programs stored in the OM3 or the built-in ROM 12 are executed.

When the abnormality detector 2 detects an abnormality while the system is operating, the CPU 1 receives an interrupt request signal 21.
Requests interrupt processing to 1. When the CPU 11 recognizes this interrupt request, it starts the execution of a predetermined failure recovery processing program stored in the built-in ROM 12 in advance, and performs processing for returning the system to normal operation. At this time, a process of switching the stack memory from the external RAM 4 to the internal RAM 13 is also performed.

FIG. 2 is a flow chart showing the processing contents of the CPU 11, showing the control procedure from the power-on to the standby state and from the failure recovery processing to the standby state. When the power is turned on, step S
The process starts from 1. On the other hand, the interrupt processing of the failure recovery processing starts from step S8. External bus 1
The control program up to step S4 for validating 9 is fetched from the built-in ROM 12.

<Activation by turning on the power> The microcomputer 1 is activated when the default external bus 19 is invalid.

In step S1, the logic level of the output port of the reset signal 22 is set to the reset state. After that, the devices other than the microcomputer 1 hold the reset state until step S5 at which the reset signal 22 is set to the active level. In addition, a memory area required for software operation such as a stack is provided in the internal RAM 13
Set inside.

In step S2, the variable COUNT is defined in the internal RAM 13 and its value is initialized to 0.

In step S3, the setting inside the microcomputer 1 is changed from the default state to the desired state.

In step S4, the external bus control unit 15 is set so that the external bus 19 becomes valid. At the same time, the setting of variables such as the stack pointer necessary for executing the program is changed to the address value corresponding to the external RAM 4.

In step S5, the logic level of the output port of the reset signal 22 is set to the active state. As a result, the reset state of the devices other than the microcomputer 1 is released, and the reading unit 5, the recording unit 6, the communication unit 7, and the operation unit 8 which incorporate the slave CPU independently start the initialization processing.

As a result, in the case of the reading unit 5, the document conveying system, the reading light source system that moves in the sub-scanning direction, and the recording unit 6 are provided.
In this case, the mechanical drive units such as the paper transport system and the recording process are initialized and driven, and this is heard by the user as a machine operating sound. Further, the reason why the initialization is being performed is displayed on the display unit provided in the operation unit 8.

At step S6, the microcomputer 1 controls initialization of each part of the system.

In step S7, when the program reaches this step, it is determined that the system can be started normally, the contents of the variable COUNT are initialized to 0, and the system shifts to the standby state.

<Abnormality Detection Interrupt Processing> Step S8
Then, the logic level of the output port of the reset signal 22 is set to the reset state. Thereafter, devices other than the microcomputer 1 set this signal to the active level S
The reset state is held until 5. In addition, a memory area required for software operation such as a stack is stored in the internal RAM 1
Set to 3.

In step S9, it is determined whether the value of the variable COUNT defined inside the internal RAM 13 is larger than the predetermined value n. If it is larger, the process proceeds to step S11, and thereafter, the cancellation process is performed. On the other hand, if equal or smaller, the process proceeds to step S10 and system restart processing is performed.

In step S10, the value of the variable COUNT is set to 1
to add. This variable is 0 when shifting to the standby state.
Since the initialization is performed, the count value represents the number of times that the interrupt due to the abnormality detection occurs again after the restart process is started and before the initialization process is completed. After that, the process proceeds to step S3, which is the same as when power is turned on.

In step S11, since the value of the variable COUNT is larger than the predetermined value n, it is considered that the abnormality detection has been performed n times consecutively before the restart processing is completed, and the restart of the system is abandoned. Then, in order to maintain a safe stop state, the external bus control unit 15 disables the external bus 19, that is, stops the electric driving, and only supplies the bias for fixing the potential by the pull-up resistor or the pull-down resistor. .

After that, step S12 is a permanent loop until the power is turned off. However, if it is left as it is, it cannot be discriminated from the outside whether the microcomputer 1 is stopped or the restart is intentionally stopped. Therefore, it is periodically changed by using the general-purpose output port so that it can be visually recognized. Output a signal. Based on this signal, the LED provided on the operation panel or the control board is made to blink.

As described above, if there is a failure in the external system bus, the program processing will fail when the external bus is used in steps S4 to S7. This means that the variable COUNT is not initialized to 0 and is gradually added.

Once the standby state can be reached,
At least if the user inputs some operation instructions,
Until the automatic reception operation is started, the facsimile apparatus can maintain a stable state, and it is possible to avoid an abnormal operation that simply repeats the initialization operation.

[0050]

As described above, according to the present invention,
When an abnormal operation of the microcomputer system is detected, the CPU has a built-in storage area necessary for executing the failure recovery processing program in the microcomputer.
Since the failure recovery processing program stored in the built-in ROM is set to AM, the failure recovery processing program can be executed normally even if an external bus fails. The effect is that the safety of the system can be improved.

Further, by restarting the system by the fault recovery processing program, the system is restarted according to the contents of the activation factor information area which is initialized at the normal startup and the predetermined value is written during the fault recovery processing. Therefore, it is possible to prevent the system initialization operation from being repeated unnecessarily.

When stopping the system restart,
By disabling the external bus, it is possible to prevent the damage from spreading due to the failure of the external bus.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of a facsimile apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart at power-on and when a fault is recovered.

[Explanation of symbols]

1 Microcomputer device 2 Abnormality detector 3 External ROM 4 External RAM 5 Reader 6 recording section 7 Communication section 8 operation part 11 CPU 12 Built-in ROM 13 Built-in RAM 14-port control unit 15 External bus controller 16 Built-in peripheral function block 17-terminal function controller 18 internal bus 19 external bus 20 General-purpose I / O port terminal group 21 Interrupt request signal 22 Reset signal 23 Control signals for built-in peripheral functions

Claims (5)

[Claims] 1. A CPU that executes a program, and a built-in RO that stores a program including a failure recovery processing program.
A microcomputer in which M and a built-in RAM are internally connected via an internal bus, at least one external device connected to the microcomputer via an external bus and accessible by the CPU, and abnormal operation of the system. When detecting, an abnormality detection unit that outputs an interrupt request signal to the microcomputer is provided, and the CPU sets a storage area necessary for executing the failure recovery processing program in the built-in RAM according to the interrupt request signal. Then, the microcomputer system characterized by executing the failure recovery processing program. 2. The internal RAM is provided with a startup factor information area which is initialized by the CPU at the time of normal startup and in which a predetermined value is written during the failure recovery processing.
2. The microcomputer according to claim 1, wherein during the execution of the failure recovery processing program, the restart of the system by the failure recovery processing program is stopped according to the contents of the activation factor information area. system. 3. When the restart of the system is stopped,
The microcomputer system according to claim 2, further comprising external bus control means for disabling the external bus. 4. When the restart of the system is stopped,
3. The microcomputer system according to claim 2, further comprising an informing unit for informing a user of the suspension of the restart. 5. The CPU sets the external device to a reset state to initialize the inside of the microcomputer in the execution of the fault recovery processing program, and after the inside of the microcomputer is initialized, 2. The microcomputer system according to claim 1, wherein the external device is set to an active state to initialize the external device.