JPH0727480B2 - Microcomputer - Google Patents

Description

The present invention relates to a microcomputer that sequentially executes programs stored in a memory.

(B) Conventional Technology Generally, a microcomputer stores predetermined processing contents in a ROM.
It is incorporated in various electronic devices as a controller that performs a specific process by writing it in advance.

Special points to note when designing a device that controls electronic equipment using such a microcomputer are:
How to prevent the occurrence of abnormal operation. The cause of abnormal operation of the microcomputer is mainly due to momentary power failure or external noise, but hardware is generally provided with measures to prevent such influence. However, the fluctuation of the power supply voltage may be slow, or unexpectedly strong noise may occur, and it may be impossible to secure sufficient reliability against abnormal operation only by taking measures by hardware.

Therefore, a means for immediately detecting an abnormal operation and stopping or restarting the operation is also used. For example, a watchdog timer is used to detect the occurrence of abnormal operation. This is provided with a counter of a predetermined number of bits, a circuit that generates a timing signal that counts up this counter at fixed time intervals, and a circuit that resets the microcomputer when the count value reaches a predetermined value. A process for resetting the timer is inserted at a predetermined time interval. Therefore, when the program is operating normally, the timer will not expire and the microcomputer will not be reset.However, if the program malfunctions for some reason, the program will not run correctly and the timer will be reset. When a certain period of time elapses without executing the process, the timer expires and the microcomputer is forcibly reset.

(C) Problem to be Solved by the Invention However, the conventional microcomputer that detects an abnormal operation using such a watchdog timer has the following problems.

FIG. 2 is a flowchart showing an example of the processing procedure of the microcomputer. If the microcomputer is powered on and the ACL circuit is activated, the microcomputer automatically starts execution from the execution start address, first performs a predetermined initialization, and then performs the process A (n1 → n).
2). Then, the timer of the watchdog timer is reset to make a predetermined condition judgment (n3 → n4). If this determination is ON, the process B is performed and the process returns to n2 again (n5 → n2). If YES in the condition judgment of n4, process C is performed and the timer is reset (n6 → n7). If the timer is reset at an appropriate timing in this way, the watchdog timer cannot be forcibly reset, but if for some reason the microcomputer starts running in the middle of the program, depending on the conditions, Without a complete runaway,
The process to reset the timer may be performed normally. For example, in the example shown in FIG. 2, execution may be started from n2 and n2 to n5 may be executed without initializing n1. However, since the initial setting of n1 has not been performed, the condition judgment of n4 may always be NO, and this loop may be repeated forever. In order to solve such a problem, it is necessary to provide a program for detecting that the execution start address at startup is normal, but for that purpose, the entire program becomes complicated and its capacity is also increased. There was a problem of increase.

An object of the present invention is to provide a microcomputer capable of detecting whether or not execution is started from a normal address at the time of start-up and preventing continuation of an abnormal operation.

(D) Means for Solving the Problem The microcomputer of the present invention is an address coincidence detecting means for performing coincidence detection between a predetermined normal execution start address at startup and the contents of the program counter, and the address coincidence detecting means. Of the detection result storage means for storing the detection result of, and the content of the detection result storage means is checked at a predetermined check timing after activation, and the address coincidence detection means compares the normal execution start address with the content of the program counter. And a reset signal generating means for generating a reset signal when no match is detected.

(E) Function In the microcomputer of the present invention, the address match detection means detects a match between the predetermined normal start address at the time of startup and the contents of the program counter, and the detection result storage means detects the address match detection means. The result is stored, the reset signal generating means checks the content of the detection result storing means at a predetermined check timing after starting,
A reset signal is generated when the address match detection means does not detect a match between the normal execution start address and the contents of the program counter. As a result, the execution is not started from the normal execution start address when the microcomputer is started for some reason, so the contents of the detector result storage means are checked at the check timing, and the reset signal is generated. This reset signal restarts the microcomputer,
The microcomputer will start execution from the normal execution start address. That is, according to the invention of the present application, continuation of the abnormal operation due to the fact that the execution is not started from the normal address at the time of startup is surely prevented, and the normal state is automatically restored.

(F) Embodiment FIG. 1 is a circuit diagram of a main part of a microcomputer according to an embodiment of the present invention. In the figure, 1 is a program counter, 2 is a NOR gate, 3 is a latch circuit, 4 is an inverter, and 5 is an AND gate. The program counter 1 has a 10-bit configuration in the example shown in the figure, stores the address of an instruction to be executed by the CPU, and automatically counts up (+1) at the instruction execution stage. However, in the case of a jump instruction, the jump destination address is stored at the execution stage. NO
The R gate 2 calculates the NOR of each bit of the program counter 1. Therefore, the contents of program counter 1 is 000000
Only when it is 0000, the output is set to 1. The latch circuit 3 temporarily stores the output state of the NOR gate 2. AND gate 5 is a negative signal of latch circuit 3 and program counter 1
The logical product with the 2nd bit (3rd bit from the least significant bit) of
The result is generated as a reset signal for the microcomputer.

In the configuration described above, the program counter 1 and the NOR gate 2 correspond to the "address coincidence detecting means" according to the present invention, the latch circuit 3 corresponds to the "detection result storing means", the inverter 4 and the AND gate 5 and The program counter 1 (particularly the bit cell of the second bit thereof) corresponds to "reset signal generating means". That is, when the microcomputer is powered on and the ACL (auto clear) circuit is activated, the contents of the program counter 1 becomes 0000000000, so the output of the NOR gate 2 becomes 1 and the state is stored in the latch circuit 3. It Therefore, the output of the inverter 4 is zero. Therefore, the programs are sequentially executed after that, and the second bit of the program counter 1
Even if becomes 1, the output of the AND gate 5 remains 0 and the reset is not performed.

If it is a normal execution start address at startup, ie 00000000
When the execution is not started from 00, the output of the NOR gate 2 becomes 0 and the state is stored in the latch circuit 3.
After that, if the content of the second bit of the program counter becomes 1, the output of the AND gate becomes 1 and the entire microcomputer is forcibly reset. As a result, the content of the program counter 1 becomes 0000000000, and execution is started from a normal address.

In the embodiment, the example in which the entire microcomputer is forcibly reset when an abnormal state is detected,
In addition, for example, the program may be stopped and the abnormal state may be notified.

(G) Effect of the Invention As described above, according to the present invention, the reset signal is automatically generated by detecting that the execution has not been started from the normal execution start address that should be started at the time of startup. Therefore, the program does not become complicated and its capacity does not increase, and it is possible to reliably prevent an abnormal operation due to the failure to start normally and to automatically restore the normal state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a microcomputer which is an embodiment of the present invention. FIG. 2 is a flowchart showing an example of a processing procedure performed by a conventional microcomputer using a watchdog timer.

Claims (1)

[Claims] 1. An address coincidence detection means for performing coincidence detection between a predetermined normal execution start address at startup and the contents of the program counter, and a detection result storage means for storing the detection result of the address coincidence detection means. When the content of the detection result storage means is checked at a predetermined check timing after activation, and the address match detection means does not detect a match between the normal execution start address and the content of the program counter, a reset signal A reset signal generating means for generating a signal, and a microcomputer.