JPS6337613A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6337613A JPS6337613A JP17992086A JP17992086A JPS6337613A JP S6337613 A JPS6337613 A JP S6337613A JP 17992086 A JP17992086 A JP 17992086A JP 17992086 A JP17992086 A JP 17992086A JP S6337613 A JPS6337613 A JP S6337613A
- Authority
- JP
- Japan
- Prior art keywords
- film
- impurity
- soi layer
- impurity concentration
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052787 antimony Inorganic materials 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 239000007790 solid phase Substances 0.000 abstract description 3
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000348 solid-phase epitaxy Methods 0.000 description 2
- 102000006822 Agouti Signaling Protein Human genes 0.000 description 1
- 108010072151 Agouti Signaling Protein Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010065954 Stubbornness Diseases 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に係り、′＃に絶縁膜
上Ｓ１結晶基板（Ｓ ＯＩ ： Ｓｉ１ｉｃｏｎ Ｑｎ
ｉｎｓｕｌａｔｏｒ ）の製造方法に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device, in which an S1 crystal substrate on an insulating film (S OI: Si1icon Qn
insulator).
従来、Ｓｉへ上の固相成長（ＳＰＥ：５ｏｌｉｄｐｈａ
ｓｅ Ｅｐｉｔａｘｙ ）において、特に不純物を多量
に添加した場合の増速成長てついて、第１７回置体素子
材料コンファレンス、東京＋１９８５年）。Conventionally, solid phase epitaxy (SPE) on Si
Se Epitaxy), 17th Mounting Element Materials Conference, Tokyo + 1985), especially regarding accelerated growth when large amounts of impurities are added.
のレイトニュースの第８頁から第９頁（Ｔｅｃｈ。Pages 8-9 of Late News (Tech.
１）ｉｇ、（１ａｔｅ Ｎｅｗｓ ） ｏｆ ｔｈｅ
ｌ ７ ｔｈ Ｃｏｎｆｅｒｅｎｃｅｏｎ ５ｏｌｉｄ
３ｔａｔｅ Ｄｅｖｉｃｅｓ ａｎｄ Ｍａｔｅｒｉ
ａｌｓ。1)ig, (1ate News) of the
l 7th Conference 5olid
3tate Devices and Materi
als.
’［ｏｋｙｏ、Ａｕｇ、２５−２７． １９８５．
ｐｐ、 ８−９ １ において論じられている。'[okyo, Aug, 25-27. 1985.
Discussed in pp. 8-91.
これは、Ｓｉ基板の種上に波音した無定形、あるいは多
結晶Ｓｉ膜が、固相成長して単結晶て変化し、かつ１種
の周囲である５１０２上へ横方向へ成長する場合だ、こ
のＳｉ膜て予め不縄ｍを１×１０２０／ｃｍ３以上添加
すると横方向成長が増速される現象を述べたものである
。This is a case where an amorphous or polycrystalline Si film grown on a Si substrate seed undergoes solid phase growth, changes to a single crystal, and grows laterally onto the surrounding area 5102. This describes a phenomenon in which lateral growth is accelerated when 1×10 20 /cm 3 or more of non-conformity is added to this Si film in advance.
しかし、不純物をＩ Ｘ １０” ／ｅｊ以上添加する
とこのＳ ｉＯｘ上Ｓｉ膜（以下ＳＯＩ漠と略す）は、
不純物濃度が高すぎて、通虜のＭＯＳトランジスタのチ
ャネルや、バイポーラトランジスタのベース領域として
用いることはできない、ＶＯＳトランジスタであれば少
なくと％ Ｉ Ｘ １０”、’ｃｔｄ以下てする必要が
ある。However, when more than I x 10"/ej of impurities are added, this Si film on SiOx (hereinafter abbreviated as SOI) becomes
The impurity concentration is too high to be used as the channel of a conventional MOS transistor or the base region of a bipolar transistor.For a VOS transistor, the impurity concentration must be at least % I x 10'','ctd or less.
本発明の目的は、ＳＯＩ膜の不純物濃度をｌＸｌ０”／
ｃＩＡ以上に高めて、その増速成長を利用し、かつ、ト
ランジスタが形成できるＩ Ｘ １０”／ｍ以下の不純
物濃度のＳＯＬ−を得ることである。The purpose of the present invention is to reduce the impurity concentration of the SOI film to lXl0”/
The goal is to increase the impurity concentration to more than cIA, take advantage of the accelerated growth, and obtain SOL- with an impurity concentration of I x 10''/m or less at which a transistor can be formed.
上記目的は、一旦５ＯＩｒ−の不純物Ｉｌｋ度をＩ×１
０２０ ／−以上にして増速成長を行なわしめた上。The above purpose is to once reduce the impurity Ilk degree of 5OIr- to I×1
020/- or more to perform accelerated growth.
ＳＯＩ層中の不純物を飛散してその濃度を減少すること
により達成される。This is achieved by scattering impurities in the SOI layer to reduce their concentration.
以下本発明の詳細な説明する。まず第２図に示すように
、（１００）８ｉ基板１上によく知られた熱酸化法など
で０．５μｍ厚の５ｉＯｚｉ！を形成する。その後、種
結晶部８のＳｉ基板１がむき出しとする領域をエツチン
グで形成する。この後第２図に示すように０．５μｍ厚
の多結晶あるいは無定形Ｓｉ！をＣＶＤ法や真空蒸着法
で被着しＳＯＩＯｓＯ４る。このＳｉ膜の被着と同時、
あるいは被着後に、Ａｓ、ｐ、ａ、 Ｓｂ等の不純物を
１×１０２０／−以上の濃度に添加する。The present invention will be explained in detail below. First, as shown in FIG. 2, 0.5 μm thick 5iOzi! form. Thereafter, a region of the seed crystal portion 8 where the Si substrate 1 is exposed is formed by etching. After this, as shown in Figure 2, 0.5 μm thick polycrystalline or amorphous Si! SOIOsO4 is deposited by CVD or vacuum evaporation. Simultaneously with the deposition of this Si film,
Alternatively, after deposition, impurities such as As, p, a, and Sb are added to a concentration of 1×10 20 /- or more.
その後、６００Ｃで熱処理すると１種結晶部８から、Ｓ
ＯＩＯｓＯ４結晶化が始まり、５ｊＯｚ膜２の上て単結
晶がはい上って、橋結晶部８から少なくとも２０μｍの
距Ａｌｌまで単結晶となる。After that, when heat treated at 600C, S
OIOsO4 crystallization begins, and the single crystal crawls up on the 5jOz film 2, becoming a single crystal up to a distance All of at least 20 μm from the bridge crystal portion 8.
このり、ＨｚやＮ２雰囲気あるいは真空中で８００Ｃ以
上の熱処理を行うと、すでに添加してあったＡｓ、Ｐ、
Ｂ、Ｓｂ等の原子が、上記ガスあるいは真空中へ飛散し
、トランジスタを形成するに必要な１×１０１９／ｃｍ
３以下の不純物濃度てなる。残存した不純物がｎ型、す
なわち、ＡＳＩＰ。Furthermore, when heat treatment is performed at 800C or higher in Hz, N2 atmosphere or vacuum, As, P, and
Atoms such as B and Sb are scattered into the above gas or vacuum at a rate of 1×1019/cm, which is necessary to form a transistor.
The impurity concentration is 3 or less. The remaining impurities are n-type, that is, ASIP.
Ｓｂなら、このま＼このＳ ＯＩ ７−にｐチャネルＭ
ＯＳ トランジスタが形成でき、Ｂであればｎチャネ
ルＭＯＳトランジスタが形成できる。If it is Sb, p channel M will be added to this SOI 7-
An OS transistor can be formed, and if B is used, an n-channel MOS transistor can be formed.
不純物濃度を精密に制御するには、一旦上記の不純物を
抜いた後、必要なだけ再びイオン打込み法などで添加す
ればよい。In order to precisely control the impurity concentration, the above-mentioned impurities may be removed once and then added again as needed by ion implantation or the like.
その後、第１図に示すように熱酸化法などで。Thereafter, as shown in FIG. 1, by a thermal oxidation method or the like.
Ｓ Ｑ ｎｍ厚のノー）ＳｊＯ鵞膜４を形成し、所定の
部分にＰを添加した多結晶ＳＬのゲート５を被着し、こ
のゲート５をマスクにｔ Ａ Ｓをイオン打込みし、Ｓ
ＯＩ層３Ｐにソース・ドレイン９を形成する。その後Ｃ
ＶＤ法で、リンを４モルチ含んだＰＳＧの眉間絶＃＆膜
６を０．５μｍ１ｌＫ被着する。・その後１層間絶縁膜
６にコンタクト孔を形成し。A SJO film 4 with a thickness of S
A source/drain 9 is formed in the OI layer 3P. Then C
A 0.5 μm 11K film of PSG containing 4 mol of phosphorus is deposited using the VD method. - After that, a contact hole is formed in the first interlayer insulating film 6.
１．０μｍ厚のＡ／、膜のソース・ドレイン電極７を被
着し、ｎチャネルトランジスタを形成する。A 1.0 μm thick A/2 film source/drain electrode 7 is deposited to form an n-channel transistor.
以上説明した実施例では、ＳＬ基板１を４結晶と単結晶
のＳＯＩＯｓＯ４たが、下地の形状や表面の結晶状態て
よって種結晶がなくても単結晶が得られるＳＯＩにおい
ても、同様に本発明を適用することができる。In the embodiments described above, the SL substrate 1 was made of four-crystal and single-crystal SOIOsO4, but the present invention can also be applied to SOI in which a single-crystal can be obtained without a seed crystal depending on the shape of the base and the crystal state of the surface. can be applied.
また以上述べた実施例では、ＳＯＩ層３全面から、単結
晶化を促進した不＠′＄ｌＪを飛散させたが、場汗によ
っては、一部分にはこの不純物を残存させたい場合があ
り、この時は第４図に示すように。Furthermore, in the embodiments described above, the impurities that promoted single crystallization were scattered from the entire surface of the SOI layer 3, but depending on the atmosphere, it may be desirable to leave this impurity in a part. The time is as shown in Figure 4.
５ｉ０２や５ｊｓＮａ膜で飛散防止膜１０を所定の部分
に被着しておけばよい。The anti-scattering film 10 may be applied to a predetermined portion using a 5i02 or 5jsNa film.
本発明によれば絶縁膜上固相成長ノーを拡大することが
でき、かつこのＳＯＩ層中にｎチャネルやｐチャネルト
ランジスタを形成できるので、ＬＳＩを形成するのに大
きな効果がある。According to the present invention, the size of solid phase growth on an insulating film can be expanded, and n-channel or p-channel transistors can be formed in this SOI layer, which is very effective in forming LSIs.
【図面の簡単な説明】
第１図は本発明の一実施例の縦ｉｆｒ面図、第２〜第３
図は本実施例を説明する断面図、第４図は他の実施例の
断面図である。
１・・・Ｓｉ基板、２・・・８１０２膜、３・・・ＳＯ
Ｉ層、４・・・ノー）ＳｉＣｈ膜、５・・・ゲート、６
・・・層間絶縁膜、７・・・ソース・ドレイン電極、８
・・・種結晶部。
第 １ 図
／Ｓε基板
Ｚ Ｓ；Ｏｚ臘
て Ｚ 図
菓 ３ 口
第 ４ 国[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a longitudinal ifr view of one embodiment of the present invention, and FIG.
The figure is a cross-sectional view for explaining this embodiment, and FIG. 4 is a cross-sectional view of another embodiment. 1...Si substrate, 2...8102 film, 3...SO
I layer, 4...No) SiCh film, 5... Gate, 6
...Interlayer insulating film, 7...Source/drain electrode, 8
...Seed crystal part. Figure 1/Sε board Z
Claims (1)
０＾２＾０／ｃｍ＾３以上添加する工程、４００〜１４
００℃の熱処理によつて該Ｓｉ膜の結晶粒を拡大する工
程、ガスあるいは真空中で４００〜１４００℃で上記不
純物を飛散させ不純物濃度を１×１０＾１＾９／ｃｍ＾
３以下に低下する工程を含むことを特徴とする半導体装
置の製造方法。1. Adding impurity atoms 1×1 to polycrystalline or amorphous Si film
Step of adding 0^2^0/cm^3 or more, 400-14
A process of enlarging the crystal grains of the Si film by heat treatment at 00°C, scattering the impurities at 400 to 1400°C in gas or vacuum to reduce the impurity concentration to 1 x 10^1^9/cm^
1. A method of manufacturing a semiconductor device, comprising a step of decreasing the number of semiconductor devices to 3 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17992086A JPS6337613A (en) | 1986-08-01 | 1986-08-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17992086A JPS6337613A (en) | 1986-08-01 | 1986-08-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6337613A true JPS6337613A (en) | 1988-02-18 |
Family
ID=16074231
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17992086A Pending JPS6337613A (en) | 1986-08-01 | 1986-08-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6337613A (en) |
-
1986
- 1986-08-01 JP JP17992086A patent/JPS6337613A/en active Pending
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