JPS6148976A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS6148976A JPS6148976A JP17091484A JP17091484A JPS6148976A JP S6148976 A JPS6148976 A JP S6148976A JP 17091484 A JP17091484 A JP 17091484A JP 17091484 A JP17091484 A JP 17091484A JP S6148976 A JPS6148976 A JP S6148976A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- channel region
- region
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 16
- 230000003647 oxidation Effects 0.000 abstract description 13
- 238000007254 oxidation reaction Methods 0.000 abstract description 13
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract 1
- 238000009877 rendering Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 30
- 239000013078 crystal Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- VXUYXOFXAQZZMF-UHFFFAOYSA-N titanium(IV) isopropoxide Chemical group CC(C)O[Ti](OC(C)C)(OC(C)C)OC(C)C VXUYXOFXAQZZMF-UHFFFAOYSA-N 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、薄膜トランジスタの構造に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to the structure of a thin film transistor.
近年、７ｖ膜トランジスタ（以下ＴＰＴと記す）の、デ
バイスへの応用が急速に進んでいる。In recent years, the application of 7V film transistors (hereinafter referred to as TPT) to devices has rapidly progressed.
この理由としては、製造工程が簡単なこと、素子間分離
が、絶縁基板上に形成するので、容易に行なえること、
さらに浮遊容量が減らせるなどが考えられる。The reasons for this are that the manufacturing process is simple, the isolation between elements is easy because it is formed on an insulating substrate, and
It is also possible to reduce stray capacitance.
しかしながら、単結晶シリコンに形成するバルクＭＯ３
）ランジスタと比較すると、ＴＰＴは電荷担体が運ばれ
る半導体領域が非単結晶シリコン層（以下非単結晶Ｓｉ
層）であることから、電荷担体の移動度が低い値におさ
えられる。したがってトランジスタ特性は、第４図の破
線に示すような、しきい値電圧が高く応答速度の鈍い９
、Ｙ性である。However, bulk MO3 formed in single crystal silicon
) Compared to a transistor, a TPT has a semiconductor region in which charge carriers are transported in a non-monocrystalline silicon layer (hereinafter referred to as a non-monocrystalline silicon layer).
layer), the mobility of charge carriers is suppressed to a low value. Therefore, the transistor characteristics are as shown by the broken line in FIG.
, Y-character.
そこで特性を向上させる為に種々の工程が考えられてい
る。例えば、非単結晶８１層のレーザーアニール、ある
いは帯域溶融法による再結晶化である。しかしこれら方
法では、大面積を均一に再結晶化することは、非常に困
難であり、構成されたＴＰＴはその特性に、大きなバラ
ツキが生ずるこのような不均一性を解決する手段として
は、再結晶化を行なう前の結晶状態のままで特性を上げ
ることを考える必要がある。すなわち構造を変えること
で特性を上げる必要がある。その為の具体的な手段は、
チャネル領域の非単結晶Ｓｉ層の薄膜化である。薄膜化
を進めることで、ＴＦＴは、低ゲート電圧で、オン状態
となり、しきい値電圧が下がり、オン電流が増加し、応
答速度およびオン／オフ比等の特性の向上が可能となる
。Therefore, various processes are being considered to improve the characteristics. For example, laser annealing of a non-single crystal 81 layer or recrystallization using a zone melting method. However, with these methods, it is very difficult to uniformly recrystallize a large area, and the constructed TPT has large variations in its properties. It is necessary to consider improving the properties while maintaining the crystalline state before crystallization. In other words, it is necessary to improve the characteristics by changing the structure. The specific means for that purpose are
This is to reduce the thickness of the non-single crystal Si layer in the channel region. By making the film thinner, the TFT is turned on with a lower gate voltage, the threshold voltage is lowered, the on-state current is increased, and characteristics such as response speed and on/off ratio can be improved.
しかし従来のＴＰＴの製造方法は、非単結晶８１層の熱
酸化によるゲート酸化膜形成の際、非単結晶Ｓｉ層全面
を熱酸化する為、熱酸化後の非単結晶８１層膜厚は、ソ
ース領域・ドレイン領域・チャネル領域すべて等しくな
る。故に、チャネル領域の熱酸化後の非単結晶８１層膜
厚を薄くしてＴＵＦＴを作製すると、ソース領域・ドレ
イン領域の非単結晶Ｓｉ層が薄い為、゛１＋ｉ、極材料
とのコンタクト形成の際必要となるコンタクトホールの
形成が困難となる上、コンタクト抵抗およびソース領域
・ドレイン領域の抵抗が増大し、ＴＦｌ１３性が、制約
されるという問題点があった。However, in the conventional TPT manufacturing method, when forming the gate oxide film by thermal oxidation of the non-single crystal 81 layer, the entire surface of the non-single crystal Si layer is thermally oxidized, so the thickness of the non-single crystal 81 layer after thermal oxidation is The source region, drain region, and channel region are all equal. Therefore, if a TUFT is fabricated by reducing the thickness of the non-single crystal 81 layer after thermal oxidation in the channel region, since the non-single crystal Si layer in the source and drain regions is thin, In addition, it is difficult to form a contact hole, which is necessary for this purpose, and the contact resistance and the resistance of the source region and drain region increase, resulting in a problem in that the TF113 property is restricted.
本発明はこのような問題点を解決するもので、その目的
とするところは、非単結晶Ｓｉ、４の熱酸化によりゲー
ト絶縁膜形成の隙、窒化シリコンをマスクとして用い、
非単結晶Ｓｉ層のチャネル領域を選択的に熱酸化し、ソ
ース領域・ドレイン領域の熱酸化後の非単結晶８１層膜
厚は厚く、チャネル領域は荀＜シて、コンタクト特性・
トランジスタ特性等の良好なＴＩＰＴの構造を提供する
ことにある。The present invention is intended to solve these problems, and its purpose is to remove gaps in gate insulating film formation by thermal oxidation of non-single crystal Si, 4, using silicon nitride as a mask,
The channel region of the non-single-crystal Si layer is selectively thermally oxidized, and the thickness of the non-single-crystal 81 layer after thermal oxidation of the source and drain regions is thicker, and the channel region has better contact characteristics and
The object of the present invention is to provide a TIPT structure with good transistor characteristics.
本発明は絶縁基板上に、非単結晶８１層および絶縁層を
、層構造にして構成されるＴＩＰＴの、非単結晶Ｓｉ層
に形成されるソース領域とドレイン領域間のチャネル領
域の膜厚を、窒化シリコンをマスクとして用いた、選択
的熱酸化により、局所的に薄くした構造を有することを
特徴とする。The present invention aims to reduce the film thickness of a channel region between a source region and a drain region formed in a non-single crystal Si layer of a TIPT having a layered structure of 81 non-single crystal layers and an insulating layer on an insulating substrate. , is characterized by having a structure that is locally thinned by selective thermal oxidation using silicon nitride as a mask.
以下、本発明について実施例に基づき説明する第１図に
、従来の製造工程により形成された一般的なでＦＴの構
造を、第２図に、本発明に基づき形成したＴＰＴの構造
を示す。Hereinafter, the present invention will be explained based on an example. FIG. 1 shows the structure of a general FT formed by a conventional manufacturing process, and FIG. 2 shows the structure of a TPT formed according to the present invention.
構造上の差は、従来例では、熱酸化後の非単結晶８１層
膜厚が均一であるが、本発明によるＴＰＴは、ソース領
域・ドレイン領域のコンタクト形成部では厚く、チャネ
ル領域では薄くなっていることにある。また選択的熱酸
化のマスクに使用したｆｆｌ化シリコン層は、コンタク
トホール形成時に、眉間絶縁膜６と同時にエツチングす
れば、コンタクト特性に問題とならないので、選択熱酸
化後エツチングする必要はなく、工程の上でも簡略に行
なうことができる。The difference in structure is that in the conventional example, the thickness of the non-single crystal 81 layer after thermal oxidation is uniform, but in the TPT according to the present invention, it is thicker in the contact formation part of the source region and drain region, and thinner in the channel region. It is in the fact that Furthermore, if the ffl silicon layer used as a mask for selective thermal oxidation is etched at the same time as the glabellar insulating film 6 when forming the contact hole, it will not cause any problem with the contact characteristics, so there is no need to etch it after the selective thermal oxidation. It can be easily done on top of.
次に、製造工程について、第３図を用いて説明する。Next, the manufacturing process will be explained using FIG. 3.
まず絶縁基板上に、化学気相成長法等により、非単結晶
８１層を形成し、エツチングして島状にする。続いて、
同様な方法により酸化シリコン居および窒化シリコン層
を形成、選択エツチングをすれば、第３図（α）のよう
になる。ここで、熱酸化を行なうと、第３図（ｂ）の様
になる。酸化膜の厚さは、処理時間等により正確に制御
できるので、熱酸化後のチャネル領域の非単結晶ｊ９
ｉ ％３の膜厚は、任意に設定できる。次に、非単結晶
Ｓ１層への不純物元素の導入により、導電性を良好にし
たゲート電極、あるいは他の導電性の優れた材料により
ゲート電極を形成し、続いて、ホウ紫あるいはリン等の
不純物元素を、非単結晶Ｓｉ層９にイオン打ち込み等に
より導入して、ソース領域・ドレイン領域を形成する。First, a non-single crystal layer 81 is formed on an insulating substrate by chemical vapor deposition or the like, and is etched into an island shape. continue,
If a silicon oxide layer and a silicon nitride layer are formed and selectively etched in a similar manner, the result will be as shown in FIG. 3(α). If thermal oxidation is performed here, the result will be as shown in FIG. 3(b). The thickness of the oxide film can be accurately controlled by controlling the processing time, etc., so that the non-single-crystal
The film thickness of i%3 can be set arbitrarily. Next, a gate electrode is formed with good conductivity by introducing an impurity element into the non-single-crystal S1 layer, or with another material with excellent conductivity. An impurity element is introduced into the non-single crystal Si layer 9 by ion implantation or the like to form a source region and a drain region.
ゲート電極５を厚く設定すれば、不純物元素のチャネル
領域への進入はないので自己整合により、ソース領域・
ドレイン領域の形成が可能となる。これらにより、第６
図（ｃ）の如く構成となる。次に、１間絶縁膜６を形成
し、コンタクトホールを開け、アルミニウム等電極材料
の形成、エツチングにより、第３図（ｄ）の如く構造の
ＴＮＴが、構成される。If the gate electrode 5 is set thick, impurity elements will not enter the channel region, so self-alignment will prevent the source region and
It becomes possible to form a drain region. With these, the 6th
The configuration is as shown in Figure (c). Next, an insulating film 6 is formed, a contact hole is opened, and an electrode material such as aluminum is formed and etched to form a TNT having a structure as shown in FIG. 3(d).
第４図に、従来の非単結晶領域が、ソース領域・ドレイ
ン領域・チャネル領域にわたって均一の膜厚で、コンタ
クトホールの形成が量産を考慮した上で、容易にでき、
しかも良好なコンタクト特性が容易に得られる程度の膜
厚（〜７ＱＯλ）のＴＰＴ特性（破＃りと、本発明の構
造で、チャネル領域が約２８０１で、ソース領域・ドレ
イン領域は前記同様的７００ＸであるＴＩＦＴの特性を
示す。Figure 4 shows that the conventional non-single crystal region has a uniform film thickness over the source region, drain region, and channel region, and contact holes can be easily formed in consideration of mass production.
Furthermore, in the structure of the present invention, the channel region is approximately 280 mm, and the source and drain regions are approximately 700 mm thick, as described above, with a film thickness (~7QOλ) that allows for easy acquisition of good contact characteristics. The characteristics of TIFT are shown below.
しきい値電圧が下がり、ドレイン電流の立ち上がりが急
峻となっていることが明確である。ゲート電圧５ｖで比
較すれば、従来のＴＩＰＴより、ドレイン電流は、５桁
以上の増加である。It is clear that the threshold voltage has decreased and the rise of the drain current has become steeper. When compared at a gate voltage of 5V, the drain current increases by more than five orders of magnitude compared to the conventional TIPT.
またオフ電流も従来の構造のものより、１桁以上下がっ
ている。The off-state current is also lower than that of the conventional structure by more than one order of magnitude.
第４図は例としてＮチャネルＴＩＦＴの特性が示しであ
るが、ＰチャネルＴＰＴについても同様の特性が出力で
きる。Although FIG. 4 shows the characteristics of an N-channel TIFT as an example, similar characteristics can be output for a P-channel TPT.
加えて、選択的熱酸化後、窒化シリコン層をエツチング
により取り去り、第５図の如く構造と、したＴＩＦＴも
可能である。このような構造にすることにより、コンタ
クトホール形成の際、二酸化シリコンのエツチングのみ
で行なうことができる。In addition, after selective thermal oxidation, the silicon nitride layer is removed by etching, and a TIFT having a structure as shown in FIG. 5 is also possible. With this structure, contact holes can be formed by etching only silicon dioxide.
以上述べたように、本発明によれば、ソース・ドレイン
・チャネル領域の膜厚が量産時に効率良く適切なコンタ
クトホール形成ができ、さらに良好なコンタクト特性を
可能にする膜厚である非単結晶Ｓｉ層を用いる従来の構
造のＴＩＦＴと比較して、窒化シリコン層をマスクとし
た、選択的熱酸化により、チャネル領域のみ、非単結晶
８１層の膜厚を薄くするという構造にしたことで、しき
い値電圧が下がり、オン電流が増加、さらに、オフ電流
が減少し、ＴＮＴ特性が大巾に向上したので、応答速度
の速いＴＮＴ特性を必要とするデバイスへの応用を可能
にするものであり、また特に１量産時にも安定した特性
を提供できるなど、多大な効果を有するものである。As described above, according to the present invention, the film thickness of the source/drain/channel region is a non-single-crystal film having a film thickness that enables efficient and appropriate contact hole formation during mass production and also enables better contact characteristics. Compared to a TIFT with a conventional structure using a Si layer, by using a structure in which the thickness of the non-single crystal 81 layer is thinned only in the channel region by selective thermal oxidation using a silicon nitride layer as a mask, The threshold voltage has been lowered, the on-state current has increased, and the off-state current has decreased, greatly improving TNT characteristics, making it possible to apply it to devices that require TNT characteristics with fast response speed. Moreover, it has great effects, especially in that it can provide stable characteristics even during mass production.
第１図は、従来の構造のＴＩＩ’Ｔ構造を示す図。
第２図は、本発明による構造を示す図。
第３図（α）〜Ｃｄ）は、一実施例を工程順に示す図で
ある。
第４図は、従来のＴＰＴ特性（破線）と、本発明のＴＰ
Ｔ特性（実線）を示す図。条件はドレイン電圧５ｖ、形
成はチャネル長が５μ犠で、チャネル幅が１０μ惧であ
る。
第５図は、窒化シリコン層を除去して、形成したＴＰＴ
の構造を示す図。
１・・・・・・絶縁基板
２・・・・・・ソースあるいはドレイン領域３・・・・
・・チャネル領域
４・・・・・・ゲート絶縁層
５・・・・・・ゲート電極
６・・・・・・層間絶縁層
７・・・・・・電極
８・・・・・・窒化シリコン層
９・・・・・・非単結晶シリコン
１０・・・イオンビーム
以 上FIG. 1 is a diagram showing a conventional TII'T structure. FIG. 2 is a diagram showing a structure according to the present invention. FIG. 3(α) to Cd) are diagrams showing one embodiment in the order of steps. Figure 4 shows the conventional TPT characteristics (dashed line) and the TP of the present invention.
A diagram showing T characteristics (solid line). The conditions are that the drain voltage is 5V, the channel length is 5μ, and the channel width is 10μ. FIG. 5 shows the TPT formed by removing the silicon nitride layer.
A diagram showing the structure of. 1... Insulating substrate 2... Source or drain region 3...
...Channel region 4...Gate insulating layer 5...Gate electrode 6...Interlayer insulating layer 7...Electrode 8...Silicon nitride Layer 9...Non-single crystal silicon 10...Ion beam or more
Claims (3)
を、層構造にして構成される薄膜トランジスタの、前記
非単結晶シリコン層に形成されるソース領域とドレイン
領域間のチャネル領域の膜厚を、局所的に薄くした構造
を有することを特徴とする薄膜トランジスタ。(1) Film thickness of a channel region between a source region and a drain region formed in the non-single crystal silicon layer of a thin film transistor configured with a layered structure of a non-single crystal silicon layer and an insulating layer on an insulating substrate A thin film transistor characterized by having a structure in which the structure is locally thinned.
は、前記チャネル領域およびその近傍上の方がその他の
領域より厚いことを特徴とする特許請求の範囲第１項記
載の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the gate insulating film on the non-single crystal silicon layer is thicker in the channel region and its vicinity than in other regions.
に、窒化シリコン層が存在することを特徴とする特許請
求の範囲第１項記載の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein a silicon nitride layer is present at least on the source region and the drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17091484A JPS6148976A (en) | 1984-08-16 | 1984-08-16 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17091484A JPS6148976A (en) | 1984-08-16 | 1984-08-16 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6148976A true JPS6148976A (en) | 1986-03-10 |
Family
ID=15913681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17091484A Pending JPS6148976A (en) | 1984-08-16 | 1984-08-16 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148976A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05127192A (en) * | 1991-11-06 | 1993-05-25 | Sharp Corp | Active matrix substrate and production thereof |
| EP0635880A1 (en) * | 1993-07-22 | 1995-01-25 | Commissariat A L'energie Atomique | Method of manufacturing a transistor using silicon on insulator technology |
| US5459347A (en) * | 1991-12-30 | 1995-10-17 | Nippon Telegraph And Telephone Corporation | Method of making field-effect semiconductor device on SOI |
| US6337232B1 (en) | 1995-06-07 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region |
| US6797550B2 (en) | 2001-12-21 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
| US6911358B2 (en) | 2001-12-28 | 2005-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
-
1984
- 1984-08-16 JP JP17091484A patent/JPS6148976A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05127192A (en) * | 1991-11-06 | 1993-05-25 | Sharp Corp | Active matrix substrate and production thereof |
| US5459347A (en) * | 1991-12-30 | 1995-10-17 | Nippon Telegraph And Telephone Corporation | Method of making field-effect semiconductor device on SOI |
| EP0635880A1 (en) * | 1993-07-22 | 1995-01-25 | Commissariat A L'energie Atomique | Method of manufacturing a transistor using silicon on insulator technology |
| FR2708142A1 (en) * | 1993-07-22 | 1995-01-27 | Commissariat Energie Atomique | Method of manufacturing a transistor in silicon on insulator technology. |
| US5439836A (en) * | 1993-07-22 | 1995-08-08 | Commissariat A L'energie Atomique | Method for producing a silicon technology transistor on a nonconductor |
| US6541795B2 (en) | 1994-06-14 | 2003-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor device and production method for the same |
| US6337232B1 (en) | 1995-06-07 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabrication of a crystalline silicon thin film semiconductor with a thin channel region |
| US6797550B2 (en) | 2001-12-21 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method therefor |
| US7319055B2 (en) | 2001-12-21 | 2008-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam |
| US6911358B2 (en) | 2001-12-28 | 2005-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7129121B2 (en) | 2001-12-28 | 2006-10-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7635883B2 (en) | 2001-12-28 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
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