JP2689865B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method, and more particularly to an insulated gate thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art As shown in FIG. 7, the structure of a conventional upper gate light / thin transistor using polycrystalline silicon as a channel is a polycrystalline silicon thin film 302 on an insulating substrate 301 in which a channel region 307, a source region 306 and a drain region are formed. 305 is formed, and the gate electrode 304 is formed on the channel region 307 via the gate insulating film 303. Increasing the crystal grain size is effective for improving the characteristics of the thin film transistor. For that purpose, the polycrystalline silicon film forming the channel in the channel region is once formed as amorphous silicon and Crystallization often occurs at temperature. The crystallinity of the polycrystalline silicon film can be further improved by performing thermal oxidation after forming the polycrystalline silicon film. As a result, for example, International Conference on Solid State Devices, and Materials 1991, 174th.
Pages 176 (International Con
reference on Solid State De
vice and Materials (1991) p
p. 174-176), the transistor characteristics are improved by thermally oxidizing the polycrystalline silicon thin film in which the channel is formed. The influence on the film quality depends on the oxidation temperature, and the increase in the crystal grain size is caused by the high temperature oxidation of 1000 ° C. or higher, and the reduction of defects in the crystal grains is the main factor in the oxidation at the relatively low temperature of 700-900 ° C. It is effective for improving the transistor characteristics.

[0003]

However, although such characteristic improvement is remarkable with respect to the initial characteristic, there is a drawback that the change is remarkable with respect to long-term reliability. It is considered that this is because the electric field is easily applied due to the film quality improvement. Therefore, even if the characteristics are significantly improved, there is a drawback that the characteristics change greatly depending on the use situation, and as a result, the variations among the elements become large.

[0004]

A feature of the present invention is that a silicon thin film having a channel region, a source region and a drain region, for example, a polycrystalline silicon film, and a source and drain electrodes respectively connected to the source and drain regions. , Contacting the channel region through the gate insulating film
In a thin film transistor having a gate electrode to
In the thin film transistor, a region having a crystal defect density higher than that of the channel region is formed near a boundary between the channel region and the drain region.
Here, a region having a crystal defect density higher than that of the channel region can be formed in the vicinity of the boundary between the channel region and the source region.

[0005]

Another feature of the present invention is a method of manufacturing a lower gate type thin film transistor in which the gate electrode is present between the silicon thin film and a substrate, after forming the silicon thin film on the gate electrode, In the method of manufacturing a thin film transistor, the portion of the silicon thin film on the end portion of the gate electrode is covered with an insulating film, and then an oxidation treatment is performed at 700 to 900 ° C.

Yet another feature of the present invention is a method of manufacturing an upper gate type thin film transistor in which the gate electrode is present on the silicon thin film on a substrate, wherein the gate electrode is present in the silicon thin film after the gate electrode is formed. A step of ion-implanting impurities that do not generate carriers into the silicon thin film, and a step of reducing the resistance of the source and drain regions after forming a sidewall made of an insulating film on the end of the gate electrode. The method for manufacturing a thin film transistor includes the above.

That is, according to the present invention, in a thin film transistor using a silicon thin film in a channel region for forming a channel and having a source electrode, a drain electrode and a gate electrode, a drain region of the silicon thin film or a channel region of the drain and source region is formed. It is characterized in that the crystallinity of the other channel portion is improved as compared with the crystallinity of the contacting end portion. Good crystallinity is specifically
This means that the collapse density is low . Further, since the crystallinity of the end portion of each region is a relative comparison of the crystallinity of the other channel portion, when the crystallinity of the channel portion excluding the gate end portion from the state where the silicon thin film is formed is improved. Not only this, but also includes the case where the crystallinity of the silicon thin film at the gate end is deteriorated.

Even if the characteristics of a thin film transistor are improved, what or what region is dominant depends on which characteristic. For example, the rise of a transistor when a gate voltage is applied is strongly influenced by the defect density in the silicon film and the interface order density, and the leak current is controlled by the defect density and the electric field strength at the end portion of the drain region. The change in characteristics when the transistor is turned on is strongly influenced by the electric field height and the degree of impact ionization at the end portion of the drain region. Therefore, the defect density of the silicon thin film at the edge of the drain region
By lowering the voltage, the electric field at the drain edge is strengthened, and carriers generated by impact ionization cause large fluctuations in characteristics. In order to improve the transistor characteristics and improve the long-term reliability, it is necessary to reduce defects in the channel portion that affect the characteristics at the time of turning on , while avoiding the electric field concentration at the end portion of the drain region. In the present invention, good characteristics can be maintained for a long period of time by keeping the crystallinity at the end portion of the drain region relatively bad.

Taking an N-channel transistor having an N-type source / drain region and a P-type channel region for enhancement as an example, the present invention has a high crystal defect density.
The region of the present invention formed in the vicinity of the boundary between the source / drain region and the channel region is poor in crystallinity.
The source and drain regions may have the same N type as the source or drain region, or the channel region with good crystallinity may have the same P type. However, in the actually manufactured transistor, the P type and N type are used, and a PN junction is formed inside this region. Often formed.

[0011]

EXAMPLES Next, the present invention will be described with reference to examples.

FIG. 1 is a vertical sectional view for explaining a first embodiment of the present invention. This embodiment is constructed as follows. A gate electrode 102, a gate insulating film 103, a silicon thin film 104, and an interlayer insulating film 105 are laminated on an insulating substrate 101, a contact hole 106 is formed in the interlayer insulating film 105, and a wiring metal 107 is provided there.

The silicon thin film 104 has a channel region 108, a drain region 109, and a source region 1 having a low defect density.
10 and high defect density at the drain end and the source end
A region 111 is formed. Area 1 with high defect density
11 and a channel region 108 having a low defect density are arranged to face the gate electrode 102 with the gate insulating film 103 interposed therebetween.

This structure, particularly the channel region 108 having a low defect density and the region 111 having a high defect density, is formed as follows. FIG. 2 shows a state after a silicon nitride film having strong oxidation resistance is deposited after the silicon thin film 120 is formed and anisotropic etching is performed. As a result, a structure is obtained in which only the region of the silicon thin film 120 that is in contact with the side surface of the gate electrode 122 via the gate insulating film 123 is covered with the sidewall-shaped silicon nitride film 125.

After the structure of FIG. 2 is formed, oxidation is performed to oxidize the silicon thin film 120 except the region covered with the silicon nitride film 125. Since the silicon thin film 120 is formed by depositing amorphous silicon and then annealing it at a temperature of 600 ° C. to polycrystallize it, an average of about 1 is obtained at the time of polycrystallization.
It has a particle size of μm. Oxidation of such polycrystalline silicon improves the crystallinity. When the oxidation is performed at 800 ° C., almost no increase in the crystal grain size is observed, and the defects in the crystal grains are significantly reduced. The crystallinity of the region covered with the silicon nitride film 125 is not improved and the defect density of FIG.
It has become a meaningless area 111. After undergoing such a process, the lower gate type thin film transistor shown in FIG. 1 is formed.

3 and 4 show changes in characteristics of a P-channel type lower gate type thin film transistor manufactured by using the method of FIG. The thickness of the deposited silicon thin film is 40 nm, which is the result when a 40 nm thermal oxide film is formed. That is, the silicon thin film of about 20 nm is changed to an oxide film.

FIG. 3 shows changes in on-current and off-current after applying a stress voltage of 6.5 V for a certain period of time. This figure shows 130 when the drain end and the source end are covered and oxidized (in the case of the embodiment of the present invention shown by the O mark) and 131 when oxidation is performed without covering (the conventional case shown by the X mark). (In the case of technology). Both of them have an on / off ratio of about 7 digits before being stressed. Although not shown in the figure, the on / off ratio was about 6 digits when no oxidation was performed. From FIG. 3, it can be seen that there is a large difference in off-state current when stress is applied for a long time. That is, the off-current 130 of the embodiments of FIGS. 3 and 4 of the present invention does not change much, but the off-current 13 of the prior art does not change.
1 changes greatly.

FIG. 4 is a diagram showing changes in the threshold voltage of the same transistor. Compared to the case where oxidation is performed without covering the drain end and the source end 131 (in the case of the conventional technique indicated by X), the case where the end is covered and oxidized 130 (in the case of the embodiment of the present invention indicated by O) ) Indicates that the change in threshold voltage is small.

FIG. 5 is a vertical sectional view for explaining the second embodiment of the present invention. This embodiment is constructed as follows. A silicon thin film 202 on the insulating substrate 201,
A gate insulating film 203, a gate electrode 204, a sidewall 205 formed on a side surface of the gate electrode, an interlayer insulating film 206, a contact hole 207, and a wiring metal 208 are provided. The silicon thin film 204 has a channel region 209, a drain region 210, and a source region 21 with a low defect density.
1, and a region 212 having a high defect density at the drain end and the source end is formed. High defect density region 21
2 and a part of the channel region 209 are the gate insulating film 20.
The gate electrode 204 is disposed so as to face the gate electrode 204.

Next, a comparative example will be described using the structure of FIG.
explain. FIG. 6 shows a silicon thin film 2 on an insulating substrate 211.
12, a gate insulating film 213 is sequentially formed, and a gate electrode 2
It is in a state where patterning is performed after forming 14.

After FIG. 6, silicon ions are implanted into the entire surface to once amorphize the region not covered with the gate electrode. Thereafter, crystallization is performed at a temperature of 700 ° C., so that the amorphous region becomes a polycrystalline silicon film having a relatively small grain size. Then, low-concentration boron is ion-implanted to form a side wall 215 of a silicon oxide film on the side surface of the gate electrode 214.

Subsequently, the upper gate type thin film transistor shown in FIG. 5 is formed according to a usual process. In the case of the upper gate type thin film transistor, the surface roughness is generated when the polycrystalline silicon thin film is oxidized, so that the characteristic improvement by the oxidation is not so large as that of the lower gate type thin film transistor. Plus comparison
If the improvement of the film quality due to oxidation is omitted as in the example, the characteristics as good as those in the first embodiment cannot be obtained. However, by increasing the defect density of the silicon thin film at the drain end (and the source end), the long-term reliability is improved as in the first embodiment.

[0023]

As described above, according to the present invention, in the thin film transistor using the silicon thin film for the channel portion , the channel density is higher than the defect density of the drain end region or both the drain end region and the source end region. Area defects
By reducing the density, it is possible to obtain a thin film transistor having improved long-term reliability as well as initial characteristics .

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

2 is a cross-sectional view showing an example of a method of manufacturing the structure shown in FIG.

FIG. 3 is a diagram showing characteristics of the first embodiment shown in FIGS. 1 and 2 in comparison with a conventional technique.

FIG. 4 is a diagram showing characteristics of the first embodiment shown in FIGS. 1 and 2 in comparison with a conventional technique.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

6 is a cross-sectional view showing an example of a method of manufacturing the structure shown in FIG.

FIG. 7 is a cross-sectional view showing a conventional thin film transistor.

[Explanation of symbols]

101, 201, 211, 301 Insulating substrate 102, 122, 204, 214, 304 Gate electrode 103, 123, 203, 213, 303 Gate insulating film 104, 120, 202, 212, 302 Silicon thin film 105, 206 Interlayer insulating film 106, 207 Contact hole 107, 208 Wiring metal 108, 209 Channel region with low defect density 109, 210, 305 Drain region 110, 211, 306 Source region 111, 212 Region with high defect density 125 Silicon nitride film 130 Drain end and source Characteristic when the end is covered and oxidized 131 Characteristic when the drain and source ends are not covered 205 Side wall 215 formed on the side surface of the gate electrode 215 Side wall formed by a silicon oxide film 307 Channel region

Claims (5)

(57) [Claims] 1. A silicon thin film having a channel region, a source region and a drain region, source and drain electrodes respectively connected to the source and drain regions, and a gate electrode in contact with the channel region via a gate insulating film. In the thin film transistor, in the crystal grain near the boundary between the channel region and the drain region
Of the defect density of the defect in the crystal grains in the central part of the channel region.
A region higher than the recess density is formed, and the region is a transistor
A thin film transistor, which is a region through which a current passes during operation . 2. A defect density of crystal grains in the vicinity of the boundary between the channel region and the source region within said channel region
A region higher than the defect density in the central crystal grain is formed,
In the area, the current passes through it when the transistor operates.
The thin film transistor according to claim 1, wherein the thin film transistor is a region . 3. The thin film transistor according to claim 1, wherein the silicon thin film is a polycrystalline silicon film. 4. A method of manufacturing a lower gate type thin film transistor, wherein the gate electrode is present between the silicon thin film and a substrate, wherein the silicon thin film is formed on the gate electrode and then on an end portion of the gate electrode. The above-mentioned silicon thin film part is covered with an insulating film, and then 700 to 9
The method for manufacturing a thin film transistor according to claim 1, wherein the oxidation treatment is performed at 00 ° C. 5. A method of manufacturing an upper gate type thin film transistor in which the gate electrode is present on the silicon thin film on a substrate, wherein impurities that do not generate carriers even if present in the silicon thin film after the gate electrode is formed. And a step of lowering the resistance of the source and drain regions after forming a sidewall made of an insulating film on the end portion of the gate electrode. Item 4. A method of manufacturing a thin film transistor according to any one of items 1 to 3.