JPH0244714A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0244714A JPH0244714A JP19443388A JP19443388A JPH0244714A JP H0244714 A JPH0244714 A JP H0244714A JP 19443388 A JP19443388 A JP 19443388A JP 19443388 A JP19443388 A JP 19443388A JP H0244714 A JPH0244714 A JP H0244714A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous
- film
- layer
- substrate
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000013078 crystal Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000002344 surface layer Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 230000007547 defect Effects 0.000 abstract description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000000407 epitaxy Methods 0.000 abstract 2
- 239000007787 solid Substances 0.000 abstract 2
- 239000000463 material Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 36
- 238000009792 diffusion process Methods 0.000 description 10
- 239000007790 solid phase Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Chemical compound O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000035484 reaction time Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、シリコン半導体集積回路用基板の製造方法に
係り、特に制御性、量産性に優れたエピタキシャル層を
低温で形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a substrate for a silicon semiconductor integrated circuit, and particularly to a method of forming an epitaxial layer at a low temperature with excellent controllability and mass productivity.
従来、シリコン薄膜の固相エピタキシャル成長技術は、
ジャパニーズ・ジャーナル・オブ・アプライド・フイジ
クス、第15巻、1431ページ〜1436ページ(1
982年) (Japan、J、Appl。Conventionally, solid-phase epitaxial growth technology for silicon thin films is
Japanese Journal of Applied Physics, Volume 15, Pages 1431-1436 (1
982) (Japan, J, Appl.
Phys、15.1431(1982)) ニおイテ論
じラレテイル様に、シリコン単結晶基板上に気相成長法
によりアモルファスシリコン膜を堆積し、その後通常の
炉で600 ’C以下でアニールすることにより基板の
結晶格子に配向してアモルファスシリコン膜をエピタキ
シャル成長させている。Phys, 15.1431 (1982)) As discussed in Laletaire, an amorphous silicon film is deposited on a silicon single crystal substrate by a vapor phase growth method, and then the substrate is formed by annealing at 600'C or less in a conventional furnace. An amorphous silicon film is grown epitaxially with the crystal lattice of the crystal lattice oriented.
また、従来、シリコン膜のへテロエピタキシャル成長技
術として、特開昭62−263627号に記載のように
、絶縁膜上にシリコン単結晶膜を堆積し、その一部をア
モルファス化した後アニールして再結晶化させている。Conventionally, as a heteroepitaxial growth technique for a silicon film, as described in Japanese Patent Application Laid-Open No. 62-263627, a silicon single crystal film is deposited on an insulating film, a part of it is made amorphous, and then annealed and reused. It is crystallized.
上記従来技術のホモエピタキシャル成長においては、0
.1〜0.3μmの比較的薄い膜のエピタキシャル成長
であり、LSIプロセスで実用的な1μm程度の膜厚に
ついては触れられていない。In the homoepitaxial growth of the prior art described above, 0
.. The epitaxial growth is a relatively thin film of 1 to 0.3 μm, and there is no mention of a film thickness of about 1 μm, which is practical in LSI processes.
また大面積における均一性、再現性、欠陥防止について
も言及されていない。Furthermore, there is no mention of uniformity, reproducibility, or defect prevention over large areas.
一方、従来技術のへテロエピタキシャル層の固相エピタ
キシャル再結晶においては、本質的にヘテロエピタキシ
ャル層を種結晶とするため、再結晶層の結晶性の向上に
限界がある。On the other hand, in the conventional solid-phase epitaxial recrystallization of a heteroepitaxial layer, since the heteroepitaxial layer is essentially used as a seed crystal, there is a limit to the improvement in crystallinity of the recrystallized layer.
本実の目的は、1μm程度の膜厚でも優れた結晶性の固
相エピタキシャル層を形成する方法を提供するにある。The purpose of the present invention is to provide a method for forming a solid phase epitaxial layer with excellent crystallinity even when the thickness is about 1 μm.
また本実の他の目的は、欠陥密度が低く、均一性、再現
性の良い固相エピタキシャル成長法を提供するにある。Another object of the present invention is to provide a solid-phase epitaxial growth method with low defect density, good uniformity, and good reproducibility.
上記目的は、次の3つの工程を施すことにより達成され
る。The above object is achieved by performing the following three steps.
1)シリコン単結晶基板にイオン打込みし、表面層をア
モルファス化させる工程。この時、結晶欠陥密度(単結
晶からアモルファス化への程度)は表面が最も大きく、
結晶内部にいくに従って減少する。1) A process of implanting ions into a silicon single crystal substrate to make the surface layer amorphous. At this time, the crystal defect density (degree of transition from single crystal to amorphous) is greatest at the surface;
It decreases as you go inside the crystal.
2)上記基板上にアモルファス化げコン膜を堆積させる
。ここで堆積させる膜の厚みは必要とするエピタキシャ
ル層の厚みである。2) Depositing an amorphous oxide film on the substrate. The thickness of the film deposited here is the thickness of the required epitaxial layer.
3)アニールすることにより固相エピタキシャル成長さ
せ、裁板表面のアモルファス層及び堆積させたアモルフ
ァス膜を単結晶化させる。3) Solid-phase epitaxial growth is performed by annealing, and the amorphous layer on the surface of the cutting plate and the deposited amorphous film are made into single crystals.
シリコン単結晶基板にイオン打込みすることにより欠陥
が発生する。その結晶欠陥密度(損傷量二打込みイオン
とシリコン結晶の原子核衝突により変位したシリコン原
子の密度で、5 X 1022an−3に達すると完全
なアモルファス層になる。)は打込みイオンの飛程のm
位長さ当りの損失エネルギーの大きさに比例するが、ド
ーズ量が大きくなると、その飛程よりや5浅い所まで完
全なアモルファス層となり、それより深い所では損傷量
は(li調に減少する。Defects occur when ions are implanted into a silicon single crystal substrate. The crystal defect density (the density of silicon atoms displaced by nuclear collision between the implanted ions and the silicon crystal, which becomes a complete amorphous layer when it reaches 5 x 1022an-3) is equivalent to m of the range of the implanted ions.
The amount of damage is proportional to the amount of energy lost per distance, but as the dose increases, a completely amorphous layer forms up to a point shallower than the range, and the amount of damage decreases to (li) at a depth deeper than that. .
この様な損傷量分布をもつ基板の表面を清浄にして、そ
の上にアモルファス膜を堆積させると、基板表面と堆積
膜ははゾ連続した相となるため。When the surface of a substrate with such a damage distribution is cleaned and an amorphous film is deposited on it, the substrate surface and the deposited film form a continuous phase.
アニールすると界面での結晶性の不連続に起因する転位
や積層欠陥、突起等の発生を防止した固相エピタキシャ
ル成長が可能となる。Annealing enables solid-phase epitaxial growth that prevents the occurrence of dislocations, stacking faults, protrusions, etc. caused by crystalline discontinuities at the interface.
以下、本発明の実施例を図面を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
実施例1 第1図(a)シリコン単結晶基板10を示す。Example 1 FIG. 1(a) shows a silicon single crystal substrate 10. FIG.
結晶の品位は、製法C72面方位(1oO)オフアンク
ル4°、導電型n型、抵抗率0.01Ω(7)。The quality of the crystal is manufacturing method C72 plane orientation (1oO) off-ankle 4°, conductivity type n type, resistivity 0.01Ω (7).
1ヘーパント及び33度アンチモン3.3 X 101
8a toms / i 、表面仕上げ超ミラー仕上げ
、直径4″φ、厚み500iLmである。尚、面方位に
オフアングルを用いたのは、イオン打込み時のチャネリ
ングを防止するためである。1 hepant and 33 degree antimony 3.3 x 101
8a toms/i, the surface finish is super mirror finish, the diameter is 4″φ, and the thickness is 500 iLm.The off-angle surface orientation was used to prevent channeling during ion implantation.
第1図(b)は上記シリコン単結晶基板10の主表面に
イオン打込みした状態を示す。イオン打込み前の基板1
0の洗浄は、フン酸でエツチングして酸化膜を除去し、
イオン打込みによる酸素のノックオンを防いだ。イオン
打込みは基板ホルダ冷却して室温以下に保ち、Ge+イ
オンを100KeV、5X10”■−2導入した。これ
により飛程600人、最大1度I X I O” at
oms/ allが得られ、また表面から約800人の
深さまでアモルファス層11が形成された。FIG. 1(b) shows a state in which ions have been implanted into the main surface of the silicon single crystal substrate 10. Substrate 1 before ion implantation
0 cleaning involves etching with hydrochloric acid to remove the oxide film.
Prevents oxygen knock-on due to ion implantation. For ion implantation, the substrate holder was cooled to keep it below room temperature, and Ge+ ions were introduced at 100 KeV and 5X10"■-2. This resulted in a range of 600 people and a maximum of 1 degree I
oms/all was obtained, and an amorphous layer 11 was formed to a depth of about 800 nm from the surface.
第1図(c)は上記基板上にアモルファスシリコン膜1
2を堆積した状態を示す。堆積面の基板の前洗浄は、有
機合剤による脱脂洗浄後、硝酸中で煮沸して表面にシリ
コン酸化膜を形成し、そのシリコン酸化膜をフッ酸で除
去して清浄表面を露出した後、雰囲気中の汚染の吸着を
避けるため過酸化水素水とアンモニア水混合液及び過酸
化水素水と塩酸混合液で洗浄し故意に室温では安定であ
るが加熱等により除去し易いシリコン酸化膜を形成した
。アモルファスシリコン膜の堆積は、モノシランS i
f−1,s を原料としたマイクロ波プラズマCVD
/i!iによる。まず、真空容器(到達圧力1×10−
7Torr)内に基板を設置する。水素及びアルゴン混
合ガスを流入して圧力3〜5 X L O−’Torr
とし、2 、45 G Hz 、 600 W (7
) 7 イ’) 0波及び最大2000Gaussの磁
場を印加して水素・アルゴンプラズマを発生させる。こ
れにより基板表面のシリコン酸化膜をスパッタエツチン
グする。FIG. 1(c) shows an amorphous silicon film 1 on the above substrate.
2 is shown deposited. Pre-cleaning of the substrate on the deposition surface involves degreasing with an organic mixture, boiling in nitric acid to form a silicon oxide film on the surface, and removing the silicon oxide film with hydrofluoric acid to expose the clean surface. In order to avoid adsorption of contamination in the atmosphere, cleaning was done with a mixture of hydrogen peroxide and ammonia water and a mixture of hydrogen peroxide and hydrochloric acid to intentionally form a silicon oxide film that is stable at room temperature but easy to remove by heating etc. . The amorphous silicon film was deposited using monosilane Si
Microwave plasma CVD using f-1,s as raw material
/i! By i. First, a vacuum container (ultimate pressure 1 x 10-
7 Torr). Flow the hydrogen and argon mixed gas to a pressure of 3 to 5 X L O-'Torr.
2,45 GHz, 600 W (7
) 7 A') Generate hydrogen/argon plasma by applying 0 waves and a magnetic field of maximum 2000 Gauss. This sputter-etches the silicon oxide film on the surface of the substrate.
続いて、真空容器内にモノシランを流入して、上記と同
様の条件で基板上にアモルファスシリコン膜を堆積させ
る。反応時間3分で厚さ1.5 μmの膜が堆積した。Subsequently, monosilane is introduced into the vacuum container, and an amorphous silicon film is deposited on the substrate under the same conditions as above. A 1.5 μm thick film was deposited in a reaction time of 3 minutes.
この時、基板温度はマイクロ波及びプラズマの照射によ
り約160’Cまで上昇した。At this time, the substrate temperature rose to about 160'C due to microwave and plasma irradiation.
第1図(d)はアニーリングにより固相エピタキシャル
成長させ、アモルファス層及び膜を単結晶13にした状
態を示す。アニーリングは700’C,30分のウェッ
ト酸素雰囲気中と、800℃、12分の乾燥窒素雰囲気
中の二段階より成る。FIG. 1(d) shows a state in which the amorphous layer and film are made into a single crystal 13 by solid phase epitaxial growth by annealing. Annealing consists of two steps: 700° C. for 30 minutes in a wet oxygen atmosphere and 800° C. for 12 minutes in a dry nitrogen atmosphere.
この様にして作成したエピタキシャル層は、膜厚1.5
μm、ウェハ内の均一性±5%、容量電圧法で求めた
不純物濃度はl X I O13cm−3、抵抗率10
0Ω−印、抵抗率のウェハ内向−性士12%以下、積層
欠陥密度はウェハ内5個以下である。The epitaxial layer created in this way has a film thickness of 1.5
μm, uniformity within the wafer ±5%, impurity concentration determined by capacitance voltage method: l x I O13cm-3, resistivity 10
0Ω- mark, resistivity of 12% or less in the wafer, and stacking fault density of 5 or less in the wafer.
実施例2
第2図、第3図は本発明の方法をバイポーラLSIに適
用した例を示す。Embodiment 2 FIGS. 2 and 3 show an example in which the method of the present invention is applied to a bipolar LSI.
第2図(a)シリコン単結晶基板2oを示す。FIG. 2(a) shows a silicon single crystal substrate 2o.
結晶の品位は、製法CZ、面方位(100)4゜オフア
ングル、導電型P型、ドーパントボロン、抵抗率1〜2
Ω−■、表面仕上げ超ミラー仕上げ、直径4″φ、厚み
500μmである。The quality of the crystal is manufacturing method CZ, plane orientation (100) 4° off angle, conductivity type P type, dopant boron, resistivity 1~2
Ω-■, surface finish super mirror finished, diameter 4″φ, thickness 500 μm.
第2図(b)は埋込みコレクタ拡散層21を形成した状
態を示す。シリコン酸化膜をマスクとしてアンチモンを
選択拡散させた。アンチモンの拡散は、三酸化アンチモ
ン5b203をソースとして、窒素雰囲気中1175°
C115分のデポジション後、酸素雰囲気中1000℃
、5o分のドライブイン拡散させたものであり、拡散深
さ1.1 μm、シート抵抗45〜5oΩ/口、表面の
酸化膜22の厚さは650人及び4000人である。FIG. 2(b) shows a state in which a buried collector diffusion layer 21 is formed. Antimony was selectively diffused using a silicon oxide film as a mask. Antimony diffusion is carried out at 1175° in a nitrogen atmosphere using antimony trioxide 5b203 as a source.
1000°C in oxygen atmosphere after 115 minutes of deposition
, 500m, the diffusion depth is 1.1 μm, the sheet resistance is 45 to 500Ω/hole, and the thickness of the oxide film 22 on the surface is 650 and 4000.
第2図(c)は酸化膜22をホトリソグラフィによりパ
ターニングした後、イオン打込みしだ状態を示す。酸化
膜22のパターンはアイソレーション成域に相当する場
所であり、幅1.0 μmである。イオン打込み条件は
、アンチモンsb+を加速電圧150KeV、ドーズ量
I X L O14an−2基板温度30’C以下とし
た。これにより、シリコン基板20の表面層のシリコン
酸化膜マスク22のない部分はアモルファス層23にな
る。FIG. 2(c) shows a state where ion implantation has begun after the oxide film 22 has been patterned by photolithography. The pattern of the oxide film 22 corresponds to the isolation region and has a width of 1.0 μm. The ion implantation conditions were an acceleration voltage of 150 KeV for antimony sb+, a dose of I X L O14an-2, and a substrate temperature of 30'C or less. As a result, the portion of the surface layer of the silicon substrate 20 where the silicon oxide film mask 22 is not formed becomes an amorphous layer 23.
第2図(d)は上記基板のシリコン酸化膜22をエツチ
ング除去した後、CVD法でアモルファスシリコン膜2
4を堆積した状態を示す。アモルファスシリコン膜24
の堆積条件は、実施例1と同様であり、ただし、ホスフ
ィンPH3をドーパントとして用いn型とし、膜厚は0
.8 μmである。FIG. 2(d) shows that after the silicon oxide film 22 on the substrate is removed by etching, an amorphous silicon film 2 is formed using the CVD method.
4 is shown deposited. Amorphous silicon film 24
The deposition conditions were the same as in Example 1, except that phosphine PH3 was used as a dopant to make it n-type, and the film thickness was 0.
.. It is 8 μm.
第2図(e)はアニーリングにより固相エピタキシャル
成長させた状態を示す。アニールの条件は実施例1と同
様である。この時、イオン打込みした部分の表面上に堆
積したアモルファスシリコン膜は導電型n型、抵抗率1
0Ω−■の単結晶膜25になるが、イオン打込み時にマ
スクされた部分の表面上に堆積したアモルファスシリコ
ン膜は完全な単結晶にはならず、多結晶膜26となる。FIG. 2(e) shows the state of solid phase epitaxial growth by annealing. The annealing conditions are the same as in Example 1. At this time, the amorphous silicon film deposited on the surface of the ion-implanted area has an n-type conductivity and a resistivity of 1.
Although a single crystal film 25 of 0Ω-■ is formed, the amorphous silicon film deposited on the surface of the portion masked during ion implantation does not become a perfect single crystal but becomes a polycrystalline film 26.
第3図(f)はアイソレーション及びベース拡散した状
態を示す。拡散は、幅1.0 μmのアイソレーショ
ン用開口部及び7μm口のベース用開口部を有する主1
−レジストをマスクとしてボロンB+をイオン打込みし
、ドライブイン拡散させたものである。アイソレーショ
ン領域は多結晶シリコンであるためボロンの拡散速度は
単結晶シリコン中に比へて数倍大きい。このためボロン
の拡散条件はベース層28を形成するための条件とする
二とにより、同時にアイソレーションWJ2’lが形成
できる。この様にアイソレーションWJ27とベース層
28用のホトリソグラフィ及び拡散を同時に実施でき工
程短縮できる。更にアイソレーション拡散層の横方内拡
がりを小さくでき高抜積化に大きく寄与できる。FIG. 3(f) shows the state of isolation and base diffusion. The diffusion was performed using a main 1 with a 1.0 μm wide isolation opening and a 7 μm wide base opening.
- Boron B+ is ion-implanted using a resist as a mask, and drive-in diffusion is performed. Since the isolation region is made of polycrystalline silicon, the diffusion rate of boron is several times higher than that in single-crystal silicon. Therefore, by setting the boron diffusion conditions to those for forming the base layer 28, the isolation WJ2'l can be formed at the same time. In this way, photolithography and diffusion for the isolation WJ 27 and the base layer 28 can be performed simultaneously, and the process can be shortened. Furthermore, the lateral inward expansion of the isolation diffusion layer can be reduced, which can greatly contribute to increasing the drawing area.
第3図(g)はエミツタ層29を形成し、更にアルミニ
ウムコンタクト30a、30b、30cを形成した状態
を示す。FIG. 3(g) shows a state in which an emitter layer 29 has been formed and aluminum contacts 30a, 30b, and 30c have been further formed.
本発明によれば、欠陥の少なく均一性のよい高品質のシ
リコンエピタキシャル層を低温で形成できる。また更に
、半導体集積回路製造プロセスにおける工程短縮、高精
度化にも寄与できる。According to the present invention, a high quality silicon epitaxial layer with few defects and good uniformity can be formed at low temperature. Furthermore, it can also contribute to shortening the process and increasing precision in the semiconductor integrated circuit manufacturing process.
第1図、第2図、第3図は本発明の実施例を示す工程毎
の断面模式図である。
10.20・・・シリコン単結晶基板、11.23・・
アモルファス層、12.24・・・アモルファス膜、第
2
図FIG. 1, FIG. 2, and FIG. 3 are schematic cross-sectional views of each step showing an embodiment of the present invention. 10.20...Silicon single crystal substrate, 11.23...
Amorphous layer, 12.24...Amorphous film, Fig. 2
Claims (1)
、 (イ)単結晶基板の表面層にイオン打込みしてアモルフ
ァス層を形成する工程 (ロ)該基板上にアモルファスシリコン膜を堆積する工
程 (ハ)上記基板をアニールすることによりアモルファス
層及びアモルファス膜を単結晶化する工程 から成ることを特徴とする半導体装置の製造方法。[Claims] 1. In forming an epitaxial layer on a single-crystal substrate, (a) forming an amorphous layer by implanting ions into the surface layer of the single-crystal substrate; (b) forming an amorphous silicon film on the substrate; A method for manufacturing a semiconductor device, comprising: (c) depositing an amorphous layer and an amorphous film into a single crystal by annealing the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19443388A JPH0244714A (en) | 1988-08-05 | 1988-08-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19443388A JPH0244714A (en) | 1988-08-05 | 1988-08-05 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0244714A true JPH0244714A (en) | 1990-02-14 |
Family
ID=16324520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19443388A Pending JPH0244714A (en) | 1988-08-05 | 1988-08-05 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0244714A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0774362A (en) * | 1993-09-06 | 1995-03-17 | Nec Corp | Thin film transistor and manufacture thereof |
-
1988
- 1988-08-05 JP JP19443388A patent/JPH0244714A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0774362A (en) * | 1993-09-06 | 1995-03-17 | Nec Corp | Thin film transistor and manufacture thereof |
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