JP2911694B2 - Semiconductor substrate and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of manufacturing the same, and more particularly, to an IGBT (Insulated) used for an inverter, a small power converter, and the like.
The present invention relates to a semiconductor substrate suitable for manufacturing a Gate Bipolar Transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art An IGBT has both the high-speed switching characteristics of a power MOSFET and the high power characteristics of a bipolar transistor, and is used as a power semiconductor element in, for example, an inverter or a small power converter.

An IGBT is generally manufactured by forming a base layer, a source layer and the like on an n ⁻ layer of a semiconductor substrate having an n ⁺ buffer layer and an n ⁻ layer formed on a p ⁺ single crystal silicon substrate. Of these, the impurity concentration of the n ⁺ buffer layer is IG
It greatly affects the operation characteristics of the BT, and it is necessary to precisely control the impurity concentration of the n ⁺ buffer layer in order to enable high-speed operation of the IGBT.

[0004] A semiconductor substrate for an IGBT is formed, for example, on one main surface of a p + single crystal silicon substrate containing high-concentration boron as a p-type impurity by forming n-concentration lower than that of the substrate.
An n ⁺ buffer layer containing n-type impurities and an n ⁻ layer containing n-type impurities at a lower concentration are sequentially grown by epitaxial growth. As described above, since the impurity concentration of the p ⁺ single crystal silicon substrate is much higher than the impurity concentration of the n ⁺ buffer layer and the n ⁻ layer, during epitaxial growth, boron is vaporized from the back surface of the substrate and the epitaxial growth layer The so-called auto doping that enters the film occurs. For this reason, a CVD oxide film is formed on the back surface of the substrate, and epitaxial growth is performed in a state where vaporization of boron is prevented.

[0005] However, even if the CVD oxide film is formed on the back surface of the substrate as described above, the impurity concentration of the substrate is extremely high, so that auto-doping from the substrate cannot be completely prevented. The impurity concentration cannot be precisely controlled. As a result, the resistivity of the n ⁺ buffer layer and the n ⁻ layer fluctuates, and the n ⁻ layer may be inverted to the p-type, which makes it difficult to manufacture a semiconductor device having good electric characteristics.

In addition, during the epitaxial growth, abnormal growth of polycrystalline projections called nodules occurs on the CVD oxide film at the peripheral portion and side end surfaces of the substrate, and the nodules are broken and separated during handling of the substrate, which may damage the epitaxial growth layer. .

Furthermore, n ^- since the base layer and the source layer of the IGBT is formed in the layer, n ^- layer needs to be epitaxially grown layer of high quality. Therefore, there was a problem that the growth rate could not be made too high, and the process time became long.

[0008] The inventors of the present invention have disclosed in Japanese Patent Application No. 3-7473.
2 proposed a new method of manufacturing a semiconductor substrate for an IGBT. N The method comprising the low-concentration n-type impurity of ^-
An n ⁺ buffer layer containing a higher concentration of n-type impurities and a p ⁺ layer containing a higher concentration of a p-type impurity are sequentially formed on a single crystal silicon substrate, and finally, the back surface of the substrate is ground and polished. Things. Here, the p ⁺ layer is grown to a predetermined thickness to secure the total thickness of the substrate, so that it can withstand handling in subsequent device processes sufficiently. In this method, the base layer and the source layer are formed on the back side of the substrate.

More specifically, as shown in FIG. 4, a diffusion method (for example, using P0Cl ₃ ) or an epitaxial growth method (for example, using P0Cl ₃ ) is applied to an n ⁻ single-crystal silicon substrate 21 (phosphorus concentration: 10 ¹⁴ cm ⁻³ or less, resistivity: 30 Ωcm or more). An n ⁺ buffer layer 22 is formed by using, for example, PH ₃ ), and a high-concentration p ⁺ layer 23 (boron concentration of 10 ¹⁸ cm ⁻³ or more and resistivity of 0.1 Ωcm or less) is epitaxially grown on the n ⁺ buffer layer 22 for IGBT. Is manufactured.

In this method, an epitaxial growth layer containing an impurity having a higher concentration than the impurity concentration of the substrate is sequentially formed, so that the influence of autodoping from the substrate during epitaxial growth can be neglected, and the impurity of the n ⁺ buffer layer can be ignored. The concentration can be precisely controlled. Also, p
^{Since the +} layer does not have a diffusion layer to be formed in a high quality silicon layer such as a base layer or a source layer, high quality is not particularly required, and high-speed growth can be performed within a range that does not become polycrystalline. . Further, it is not necessary to provide an oxide film for preventing autodoping on the back surface and side surfaces of the substrate, which not only shortens the number of steps but also reduces the number of steps.
This is a method having various effects such as no generation of nodules due to abnormal growth of polysilicon.

[0011]

In the above-mentioned method, it is necessary to deposit a p ⁺ layer as thick as several hundred μm to secure the total thickness of the substrate. For example, when using a large-diameter substrate having a diameter of 5 inches or more, the total thickness of the substrate is required to be 400 μm or more, and for that, the thickness of the p ⁺ layer is at least 2 μm.
It is necessary to deposit at least 00 μm.

However, when a dopant such as boron having a smaller atomic radius than silicon is used for the high-concentration p ⁺ layer,
When the p ⁺ layer is grown thick, the difference in the interstitial distance between boron and silicon may cause the surface of the substrate on which the p ⁺ layer is deposited to be warped concavely. For example, if the total thickness of the substrate after the grinding and polishing is required to be 400 μm or more, the p ⁺ layer must be deposited at least 200 μm or more. In this case, warpage of 150 μm or more occurs.

When a subsequent device manufacturing process is performed using a substrate having such a warp, a process failure is likely to occur. For example, when a resist is applied to a substrate in a photolithography process, the substrate does not adhere to the chuck, or even if the substrate barely adheres, problems such as pattern collapse will occur later.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor substrate capable of precisely controlling the impurity concentration of each layer and preventing the substrate from being warped, and a method of manufacturing the same.

[0015]

According to the present invention, as described in claim 1, a first conductivity type single crystal silicon substrate containing a low concentration impurity is provided. A first conductivity type first silicon layer formed on one main surface and containing an impurity at a higher concentration than an impurity concentration of the single crystal silicon substrate; and the first silicon layer formed on the first silicon layer. Of the second conductivity type containing an impurity having a higher atomic concentration and an atomic radius smaller than that of silicon.
A silicon layer, formed on the second silicon layer and containing no impurities or an impurity concentration of the second silicon layer;
And a third silicon layer of the second conductivity type containing 0.016 times or less of the impurity of the second conductivity type.

According to a second aspect of the present invention, there is provided the semiconductor substrate according to the first aspect, wherein the impurity contained in the second silicon layer is boron.

According to a third aspect of the present invention, the single crystal silicon substrate has an impurity concentration of 10 ¹⁴ cm.
^-3 or less (resistivity 30 Ωcm or more), and the impurity concentration of the first silicon layer is 10 ¹⁶ to 10 ¹⁹ cm ^-3 (resistivity 0.00
6 to 0.5 Ωcm), the impurity concentration of the second silicon layer is 10 ¹⁸ cm ⁻³ or more (resistivity 0.06 Ωcm or less), and the impurity concentration of the third silicon layer is 1.6 × 10 ¹⁶ cm.
The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a resistivity of ⁻³ or less (resistivity of 1 Ωcm or more).

Further, according to the present invention, the second silicon layer has a thickness of 10 to 120 μm, and the third silicon layer has a thickness of 30 to 200 μm. 3. A semiconductor substrate according to any one of the above items 3.

According to a fifth aspect of the present invention, there is provided a semiconductor device, comprising: a first conductive type single-crystal silicon substrate containing a low-concentration impurity; Forming a first silicon layer of a first conductivity type containing a first impurity, and forming the first silicon layer on the first silicon layer.
Forming a second silicon layer of the second conductivity type containing an impurity whose concentration is higher than the impurity concentration of the silicon layer and whose atomic radius is smaller than that of silicon; and The impurity concentration of the second silicon layer
Forming a third silicon layer of the second conductivity type containing 0.016 times or less of impurities, grinding and grinding the other main surface of the single crystal silicon substrate opposite to the one main surface to a predetermined thickness; And / or a polishing step.

Further, according to the present invention, the first silicon layer is formed by a diffusion method or a vapor growth method, and the second and third silicon layers are formed by a vapor growth method. A method for manufacturing a semiconductor substrate according to claim 5, wherein

The present invention also provides a method of manufacturing a semiconductor substrate according to claim 5 or claim 6, wherein the impurity contained in the second silicon layer is boron.

According to the present invention, the single crystal silicon substrate has an impurity concentration of 10 ¹⁴ cm.
^-3 or less (resistivity 30 Ωcm or more), and the impurity concentration of the first silicon layer is 10 ¹⁶ to 10 ¹⁹ cm ^-3 (resistivity 0.00
6 to 0.5 Ωcm), the impurity concentration of the second silicon layer is 10 ¹⁸ cm ^-3 or more (resistivity 0.06 Ωcm or less), and the impurity concentration of the third silicon layer is 1.6 × 10 ¹⁶ cm ^-3 or less ( The method for manufacturing a semiconductor substrate according to any one of claims 5 to 7, which has a resistivity of 1 Ωcm or more.

In the present invention, the thickness of the second silicon layer is 10 to 120 μm, and the thickness of the third silicon layer is 30 to 200 μm. 8. A method for manufacturing a semiconductor substrate according to any one of items 8 to 8.

[0024]

In [act invention, p comprises a sufficiently low concentration of impurity than the impurity concentration of the totally included no or p ⁺ layer further impurities on the high impurity concentration p ⁺ layer ^- thick enough to grow a layer, Since the total thickness of the substrate is ensured by the thickness of the p ⁻ layer, it is not necessary to deposit a thick p ⁺ layer having a high impurity concentration. Moreover, by depositing a low-concentration p ⁻ layer on the high-concentration p ⁺ layer, the atomic radius of the surface layer on the deposition side of the substrate becomes large. Therefore, unlike the conventional case, the substrate is not warped by thickly depositing the p ⁺ layer containing a large amount of impurities having a small atomic radius on the n-type single-crystal silicon substrate, and there is a problem in processing in a subsequent device manufacturing process. Can be reduced.

The p ⁻ layer having a low impurity concentration is unnecessary when the device is completed. However, in the conventional substrate process, the back surface of the substrate is ground and removed by about 45 to 215 μm after the device formation process is completed. Therefore, also in the present invention, the device having the same structure as that obtained by using the conventional semiconductor substrate can be finally obtained by grinding and removing the p ⁻ layer after the device forming process is completed to expose the p ⁺ layer. In other words, the p ⁻ layer is formed as a removed layer (a part for shaving) which is finally removed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a cross-sectional structure of a semiconductor substrate of the present invention. This semiconductor substrate 10 is formed by forming an n ⁺ buffer layer 12 on an n ⁻ single crystal silicon substrate 11 and finally stacking a p ⁺ layer 13 and a p ⁻ layer 14. In addition,
Although FIG. 1 shows that the n ⁻ single-crystal silicon substrate 11 surface faces upward, the source and base layers of the IGBT are formed on the n-type single-crystal silicon substrate 11 surface side in a subsequent device formation process. This is what is done.

Next, a basic manufacturing process of the semiconductor substrate of the present invention will be described with reference to FIGS. First,
400-750μ thickness mirror-finished by a known method
m, a diameter of 100 to 150 mm, and a phosphorus concentration of 10 ¹⁴ cm ⁻³ or less (resistivity of 30 Ωcm or more) on one main surface of an n ⁻ single crystal silicon substrate 11 (FIG. 2A) by a diffusion method or a vapor growth method. 3-25 μm in thickness, phosphorus concentration 10 ¹⁶ -10 ¹⁹ c
An n ⁺ buffer layer 12 having m ⁻³ (resistivity 0.55 to 0.006 Ωcm) is formed (FIG. 2B).

When the n ⁺ buffer layer 12 is formed by a vapor phase growth method, epitaxial growth is performed at a growth rate such that the n ⁺ buffer layer 12 becomes a single crystal silicon layer. In this case, since the phosphorus concentration of the n ⁺ buffer layer 12 is considerably higher than the phosphorus concentration of the n ⁻ single crystal silicon substrate 11, there is no influence of autodoping, and the phosphorus concentration of the n ⁺ buffer layer 12 can be precisely controlled. it can.

Next, a p ⁺ layer 13 having a thickness of 10 to 100 μm and a boron concentration of 10 ¹⁸ cm ⁻³ or more (resistivity of 0.06 Ωcm or less) is formed on the n ⁺ buffer layer 12 by a vapor phase growth method ( (FIG. 2 (c)). Since the p ⁺ layer 13 is not required to have high quality, it can be grown as fast as possible within the range of the single crystal silicon layer. Further, since the phosphorus concentration of the n ⁺ layer 12 is sufficiently lower than the boron concentration of the p ⁺ layer 13, the effect of the autodoping can be ignored.

Next, a p ^- layer 14 having a normal resistivity of 1 Ωcm or more and a thickness of 30 to 200 μm is formed on the p ⁺ layer 13 by a vapor phase growth method (FIG. 2D). Since the p ^- layer 14 does not require high quality, it can be grown at a high speed. Further, since the layer is finally removed, there is no inconvenience even if autodoping occurs from the substrate.

[0031] Finally, the substrate obtained in Fig. 2 (d) p ^-
After the layer 14 is polished as indicated by the broken line until the surface becomes smooth, the surface of the n ^- single crystal silicon substrate 11 is polished to a thickness of 50 to 25.
The semiconductor substrate 10 of the present invention can be obtained by performing ordinary grinding / polishing processing as shown by a broken line until the thickness becomes 0 μm (FIG. 2E). Here, the case where the n ⁻ single-crystal silicon substrate 11 surface faces upward corresponds to the semiconductor substrate 10 shown in FIG.

Next, a more specific embodiment will be described. [Example 1] As a substrate wafer, an n-type single-crystal silicon substrate having a plane orientation <100>, a phosphorus concentration of 3 × 10 ¹³ cm ⁻³ , a resistivity of 150 Ωcm, a diameter of 125 mm, and an initial thickness of 550 μm manufactured by the FZ method was used. Use vertical epitaxial
Arranged on the susceptor of the reactor.

Next, the silicon substrate is heated to 1150 ° C. in a hydrogen atmosphere, and then, phosphine diluted with hydrogen is supplied at 0.2 l / min in addition to 5 l / min of trichlorosilane and 80 l / min of hydrogen.
Deposition was performed at a growth rate of 2.0 ± 0.1 μm / min for 5 minutes to form an n ⁺ buffer layer having a thickness of 10 ± 1 μm. The amount of phosphine added is such that the silicon concentration to be deposited is 8.7 × 10 ¹⁶ cm ⁻³ and the resistivity is 0.1 ± 0.01Ω.
cm.

Next, after maintaining the substrate temperature at 1150 ° C. in a hydrogen atmosphere for 10 minutes, trichlorosilane 10 liter / min and hydrogen 80 liter / mi
0.5 liter / m of diborane gas diluted with hydrogen in addition to n
In was supplied and deposited at a growth rate of 4.0 ± 0.2 μm / min for 25 minutes to form a p ⁺ layer of 100 ± 10 μm. The amount of diborane gas added is such that the boron concentration of the silicon layer to be deposited is 2.2 × 10 ¹⁹ cm ⁻³ and the resistivity is 0.0
It was adjusted to be 0.05 ± 0.001Ωcm.

Next, trichlorosilane 10 liter / m
in and 80 l / min of hydrogen, and 4.0 ±
Deposited at a growth rate of 0.2 μm / min for 40 minutes,
A p ^- layer of 00 ± 10 μm was formed.

Next, after being taken out of the vertical epitaxial reactor, the surface of the p ^- layer is polished and smoothed by 10 μm, and the n-type single crystal silicon substrate is further polished to a thickness of 190 μm.
By grinding and polishing to a total thickness of the substrate of 410μ
m of IGBT semiconductor substrates were obtained. Then, the warpage of the obtained semiconductor substrate was measured (see FIG. 3).

Example 2 Using the same n-type single-crystal silicon substrate as in Example 1, arranging it on the susceptor of the same vertical epitaxial reactor and forming an n ⁺ buffer layer by the same process, After maintaining the temperature of 1150 ° C. in a hydrogen atmosphere for 10 minutes, trichlorosilane 10 liter / min and hydrogen 80 liter / min.
In addition, 0.5 liter / min of hydrogen-diluted diborane gas was supplied in addition to min, and deposition was performed at a growth rate of 4.0 ± 0.2 μm / min for 25 minutes to form a p ⁺ layer of 100 ± 10 μm. The addition amount of diborane gas was adjusted so that the silicon concentration of the silicon layer to be deposited was 2.2 × 10 ¹⁹ cm ⁻³ and the resistivity was 0.005 ± 0.001 Ωcm.

Next, trichlorosilane 10 liter / m
3. Diborane gas diluted with hydrogen is supplied at a rate of 0.05 L / min in addition to the hydrogen gas and hydrogen at 80 L / min.
0 ± 0.2 [mu] m / min to the growth rate in the deposition 38 min, p of 100 ± 10 [mu] m ^- to form a layer. The amount of diborane gas added was adjusted such that the silicon concentration of the deposited silicon layer was 2.7 × 10 ¹⁵ cm ⁻³ and the resistivity was 5 ± 1 Ωcm.

Next, after being taken out of the vertical epitaxial reactor, it was ground and polished under the same conditions as in Example 1, and the warpage of the obtained semiconductor substrate was measured (see FIG. 3).

Comparative Example Using the same n-type single-crystal silicon substrate as used in Examples 1 and 2, it was arranged on the susceptor of the same vertical epitaxial reactor, and the n ⁺ buffer layer was formed by the same processing. After the formation, the temperature of the substrate is set to 1
After maintaining the temperature at 150 ° C. in a hydrogen atmosphere for 10 minutes, in addition to trichlorosilane (10 L / min) and hydrogen (80 L / min), hydrogen-diluted diborane gas (0.5 L / min) was supplied. 0.2 μm
/ Min at a growth rate of / min.
A μm p ⁺ layer was formed. The amount of diborane gas added is such that the boron concentration of the silicon layer to be deposited is 2.2 × 10 ¹⁹ cm.
⁻³ , the resistivity was adjusted to be 0.005 ± 0.001 Ωcm.

Next, after being taken out of the vertical epitaxial reactor, it was ground and polished under the same conditions as in Examples 1 and 2, and the warpage of the obtained semiconductor substrate was measured (see FIG. 3).

Table 1 summarizes the growth conditions of the p ⁺ layer and the p ⁻ layer in Examples 1 and 2 and Comparative Example.

[0043]

TABLE 1 TCS H ₂ B ₂ H ₆ deposition time ρ (l / min) (l / min) (l / min) (min) (Ωcm) Example 1 p ⁺ layer 10 80 0.5 25 0.005 p ⁻ layer 1080 −40 [normal value] Example 2 p ⁺ layer 1080 0.525 0.005 p ⁻ layer 1080 0.0538 [normal value] Comparative example p ⁺ layer 1080 0.552 0.005 TCS: trichlorosilane B ₂ H ₆ : diborane

As can be seen from FIG. 3, the warpage of each of the semiconductor substrates of Examples 1 and 2 was 50 μm or less, while the warpage of the semiconductor substrate of the comparative example reached about 150 μm.

[0045]

As is apparent from the above description, according to the present invention, it is possible to obtain an IGBT semiconductor substrate in which the impurity concentration of each layer is precisely controlled and the warpage is small. As a result, troubles in the device forming process are eliminated, thereby increasing productivity and reducing costs.
A semiconductor substrate suitable for GBT applications can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a sectional structure of a semiconductor substrate of the present invention.

FIG. 2 is a process chart showing a manufacturing process of a semiconductor substrate of the present invention.

FIG. 3 is a graph showing the degree of warpage of the IGBT semiconductor substrates of the example and the comparative example.

FIG. 4 is a sectional view showing a sectional structure of a conventional semiconductor substrate.

[Explanation of symbols]

10, 20 Semiconductor substrate 11, 21 n ^- single crystal silicon substrate 12, 22 n ⁺ buffer layer 13, 23 p ⁺ layer 14 p ^- layer

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/205

Claims (9)

(57) [Claims] 1. A single-crystal silicon substrate of a first conductivity type containing a low-concentration impurity, and an impurity formed on one main surface of the single-crystal silicon substrate and having a higher concentration than an impurity concentration of the single-crystal silicon substrate. A first conductivity type first silicon layer including: and a second conductivity type impurity formed on the first silicon layer and having an impurity concentration higher than the impurity concentration of the first silicon layer and smaller in atomic radius than silicon. A second silicon layer of
It is formed on the second silicon layer and contains no impurities or 0.016 times the impurity concentration of the second silicon layer.
And a third silicon layer of the second conductivity type containing the following impurities. 2. The semiconductor substrate according to claim 1, wherein the impurity contained in the second silicon layer is boron. 3. The single-crystal silicon substrate has an impurity concentration of 10 ¹⁴ cm ⁻³ or less (resistivity of 30 Ωcm or more).
The impurity concentration of the silicon layer is 10 ¹⁶ to 10 ¹⁹ cm ⁻³ (resistivity 0.006 to 0.5 Ωcm), and the impurity concentration of the second silicon layer is 10 ¹⁸ cm ⁻³ or more (resistivity 0.06 Ωcm).
Below) and the impurity concentration of the third silicon layer is 1.6 ×
The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a resistivity of 10 ¹⁶ cm ⁻³ or less (resistivity of 1 Ωcm or more). 4. The thickness of the second silicon layer is 10-12.
0 μm, and the thickness of the third silicon layer is 30 to 200 μm
The semiconductor substrate according to any one of claims 1 to 3, wherein 5. A first silicon of the first conductivity type containing an impurity at a higher concentration than the impurity concentration of the single crystal silicon substrate on one main surface of the single crystal silicon substrate of the first conductivity type containing a low concentration impurity. Forming a layer, and forming a second conductivity type second silicon layer on the first silicon layer, the second silicon layer having an impurity concentration higher than that of the first silicon layer and having an atomic radius smaller than that of silicon. Forming a third silicon layer of the second conductivity type on the second silicon layer, which contains no impurities or contains impurities of 0.016 times or less the impurity concentration of the second silicon layer; Grinding and / or polishing the other main surface of the single crystal silicon substrate opposite to the one main surface to a predetermined thickness. 6. The method according to claim 5, wherein the first silicon layer is formed by a diffusion method or a vapor deposition method, and the second and third silicon layers are formed by a vapor deposition method. Method. 7. The method according to claim 5, wherein the impurity contained in the second silicon layer is boron. 8. The single crystal silicon substrate has an impurity concentration of 10 ¹⁴ cm ⁻³ or less (resistivity of 30 Ωcm or more),
The impurity concentration of the silicon layer is 10 ¹⁶ to 10 ¹⁹ cm ⁻³ (resistivity 0.006 to 0.5 Ωcm), and the impurity concentration of the second silicon layer is 10 ¹⁸ cm ⁻³ or more (resistivity 0.06 Ωcm).
Below) and the impurity concentration of the third silicon layer is 1.6 × 10
^The method for manufacturing a semiconductor substrate according to claim 5, wherein the semiconductor substrate has a resistivity of ¹⁶ cm ⁻³ or less (resistivity of 1 Ωcm or more). 9. The film thickness of the second silicon layer is 10-12.
0 μm, and the thickness of the third silicon layer is 30 to 200 μm
The method for manufacturing a semiconductor substrate according to claim 5, wherein