JP2813710B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a source / drain region for obtaining a MOSFET having high operation speed and high reliability.

[Conventional technology]

FIG. 3 is a view for explaining the structure of a conventional semiconductor device. FIG. 3 (a) is a plan view, and FIG. 3 (b) is a sectional view taken along line CC 'of FIG. 3 (a). It is.

In the figure, 301 is a silicon substrate, 302 is an SOI isolation silicon oxide film formed on the silicon substrate 301, and 304 is a P-type semiconductor layer formed on the oxide film 302 and having a concentration of about 5 × 10 ¹⁶ / cm ^3. , And is separated from the adjacent one by the inter-element isolation oxide film 303. Reference numeral 308 denotes a gate electrode made of polycrystalline silicon having a thickness of 0.3 μm.
It is formed via a 0 nm gate oxide film 307.

Reference numerals 305 and 306 denote a source region and a drain region, each of which is an N-type semiconductor layer having a concentration of about 1 × 10 ²⁰ / cm ³ , and are formed on both sides of the gate electrode of the P-type semiconductor layer 304. 309
Is an interlayer insulating film formed on the entire surface of the P-type semiconductor layer 304 and the device isolation oxide film 303. Contact holes 310-1, 310-310 are formed in portions corresponding to the source region 305, the drain region 306, and the gate electrode 308, respectively. 2, and 310-3 are formed, and the source region 305, the drain region 306, and the gate electrode 308 are electrically connected to the aluminum wirings 311-1, 311-2, 311-3 via the contact holes, respectively. .

 Next, the operation will be described.

In the MOSFET configured as described above, the operation speed decreases as the parasitic capacitance in the transistor structure increases. That is, the operating speed increases by reducing the parasitic capacitance. Here, the parasitic capacitance is roughly classified into the following three types. Specifically, the capacitance due to the gate oxide film, the gate capacitance due to the depletion layer which spreads by applying an electric field to the gate electrode, and the source region or the drain region There is a junction capacitance due to a depletion layer spreading near the junction between the substrate and the adjacent semiconductor layer, and a wiring capacitance due to the capacitance between the aluminum wiring and the periphery of the gate electrode and the substrate.

Focusing on the junction capacitance here, the junction capacitance is proportional to the junction area and inversely proportional to the thickness of the depletion layer. When the source and drain regions 305 and 306 are thin, the junction capacitance is the sum of the junction capacitance at the bottom of the source and drain regions and the junction capacitance at the side of the source and drain regions.

Conversely, the source and drain regions 305 and 306 are thick,
When it is in contact with the OI isolation insulating film 302, the junction capacitance is only as small as the junction capacitance at the side surfaces of the source and drain regions. The merit of the structure comes out.

[Problems to be solved by the invention]

However, in the conventional semiconductor device, the P-type semiconductor layer 304
When the thickness of the P-type semiconductor layer 304 is large, there is no problem in making the source and drain regions 305 and 306 such that the bottom surface thereof is in contact with the SOI isolation insulating film. If the drain region is so thick that its bottom surface is in contact with the SOI isolation insulating film, it will cause adverse effects on the process. That is, if the energy at the time of impurity implantation is increased, damage to the P-type silicon layer is increased, and if the heat treatment time is increased, it is difficult to form a short-channel transistor.

Therefore, in a device in which the thickness of the channel region needs to be large, the P-type semiconductor layer 304 on the SOI isolation insulating film 302
Therefore, there is a problem that it is difficult to increase the operation speed by reducing the parasitic capacitance.

Devices such as MOSFETs with a deep junction depth between the diffusion layer forming the source / drain region and the semiconductor layer around the diffusion layer, and a photo with a shallow junction depth between the diffusion layer forming the light receiving region and the semiconductor layer around the diffusion layer. When a device such as a diode is formed by a series of processes, it is necessary to change the impurity introduction depth according to the type of the device, and there is a drawback that the process becomes complicated.

The present invention has been made in order to solve the above-described problems. Even if the channel region has a large film thickness, the impurity diffusion layer can be formed without increasing the impurity implantation energy and the heat treatment time. It can be formed thick enough to reach the insulating underlayer, reducing the junction capacitance in the source and drain regions, and preventing the deterioration of the crystallinity and surface morphology of the impurity diffusion layer, thereby increasing the operating speed. Accordingly, it is an object to obtain a semiconductor device capable of improving reliability.

[Means for solving the problem]

A semiconductor device according to the present invention is formed on a surface of an insulating base layer made of an insulating material, in contact with the surface, and a first region serving as a channel region, and sandwiching the first region. A first-conductivity-type single-crystal semiconductor layer having second and third regions having crystal defect regions extending in the thickness direction; A first impurity diffusion region formed by the introduction of an impurity of the second conductivity type and having a side surface in contact with the channel region and a bottom surface separated by a predetermined distance from the surface of the insulating base layer; A source region and a drain region which are located on the side opposite to the channel region and have a second impurity diffusion region in contact with the surface of the insulating underlayer at the position of the crystal defect region; and a first impurity diffusion region of the source region. Is obtained and a gate electrode formed through a gate insulating film on a channel region of a single crystal semiconductor layer sandwiched between the side surface and the first side surface of the impurity diffusion region of the drain region.

A first region which is formed on the surface of the insulating base layer made of an insulating material and is in contact with the surface and serves as a channel region, and sandwiches the first region; A first-conductivity-type single-crystal semiconductor layer having second and third regions near the channel region having a crystal defect region formed by a plane defect perpendicular to the direction of a channel current flowing in the channel region; Formed in each of the second and third regions by introducing impurities of the second conductivity type from the surface side thereof and having a side surface in contact with the channel region and a bottom surface separated by a predetermined distance from the surface of the insulating base layer. A source region having a first impurity diffusion region and a second impurity diffusion region located on a side opposite to the channel region from the first impurity diffusion region and in contact with the surface of the insulating underlayer at the position of the crystal defect region; And a drain region, and a gate insulating film on the channel region of the single crystal semiconductor layer sandwiched between the side surface of the first impurity diffusion region of the source region and the side surface of the first impurity diffusion region of the drain region. And a gate electrode formed by the above method.

[Action]

According to the present invention, the source and drain regions formed in the single crystal semiconductor layer on the insulating underlayer have a structure having plane defects extending from the surface in the thickness direction. The impurity thus diffused in the surface defect portion to a deeper position than in other portions. For this reason, even when the single crystal semiconductor layer on the insulating base layer is thick, the source and drain regions can be partially formed without increasing the ion implantation energy for impurity introduction and the heat treatment time for impurity diffusion. It can be formed to reach the insulating underlayer below the crystalline semiconductor layer,
As a result, there is no problem in the manufacturing process, such as damage due to ion implantation and leakage of impurities into the channel region.
The junction capacitance at the bottom of the drain region can be reduced.

Further, in the present invention, the surface defect extending in the thickness direction from the surface of the source / drain region is formed at a position near the channel region so as to be perpendicular to the direction of the channel current. Since the semiconductor layer is partitioned by the above-mentioned surface defect portion, the junction capacitance which substantially acts as a parasitic capacitance can be greatly reduced. In other words, the part of the semiconductor layer thus separated, which is opposite to the channel region, is electrically separated from the channel region. Therefore, the junction capacitance between this part and the source and drain regions does not act as a parasitic capacitance, Can be reduced to only the junction capacitance with the source and drain regions in the channel region side portion of the partitioned semiconductor layer.

〔Example〕

Hereinafter, embodiments of the present invention will be described. Before describing the embodiments, the basic principle of the present invention will be described.

FIG. 1 is a diagram for explaining the basic principle of the present invention. FIG. 1 (a) is a plan view showing the structure of a MOSFET, and FIG. 1 (b) is a diagram AA in FIG. 1 (a). FIG.

In the figure, 101 to 104 and 107 to 111 are the same as those of the conventional semiconductor device shown in FIG. 3, that is, 101 is a silicon substrate, 102 is an SOI isolation insulating film, 103 is an element isolation insulating film, and 104 is a concentration. A P-type semiconductor layer of about 5 × 10 ¹⁶ / cm ³ , 107 is a gate insulating film having a thickness of about 30 nm, 108 is a gate electrode made of polycrystalline silicon having a thickness of 0.3 μm, 109 is an interlayer insulating film, 110-1,
110-2, 110-3 are contact holes, 111-1, 111-2, 11
1-3 are metal wirings.

Here, both sides of the gate electrode 108 of the P-type semiconductor layer 104 are formed as a crystal defect region 112 in which a crystal defect is introduced by being formed of a polycrystalline silicon layer. The boundary with the silicon portion is located near both ends of the gate electrode.

105 and 106 are the crystal defect regions 1 on both sides of the gate electrode.
A concentration of about 1 formed by introducing impurities in a range including 12
These are a source region and a drain region composed of an N-type semiconductor layer of × 10 ²⁰ / cm ³ .

Here, the crystal defect regions 112 in the source / drain regions 105 and 106 and the channel region therebetween are formed by first forming a polycrystalline silicon layer on the SOI isolation insulating film 102, and then forming a part of the polycrystalline silicon film. Is formed by single crystallization.

In the semiconductor device having such a structure, the diffusion speed of the grain boundary diffusion in which the impurity diffuses along the crystal grain boundary is higher than the diffusion speed of the impurity in the single crystal. Crystal defect region where many grain boundaries exist
In 112, even if the implantation energy is small and the heat treatment time is short, the implanted impurities are diffused deep by grain boundary diffusion, so that the SOI isolation insulating film below the semiconductor layer 104 is formed.
It will reach 102. That is, as is clear from FIG. 1B, the source region 105 and the drain region 1
06 each have a side surface formed in a single crystallized portion of the single crystal semiconductor layer 104 and having a side surface in contact with the channel region of the single crystal semiconductor layer 104 and a bottom surface separated by a predetermined distance from the surface of the SOI isolation insulating film 102. SOI at the position of the first impurity diffusion region and the crystal defect region 112 of the single crystal semiconductor layer 104 which is located on the opposite side of the channel region from the first impurity diffusion region.
The structure has a second impurity diffusion region in contact with the surface of the isolation insulating film 102.

As described above, the source and drain regions are formed by utilizing the grain boundary diffusion of impurities, so that even when the thickness of the semiconductor layer 104 on the SOI isolation insulating film is large, the implantation energy also increases the heat treatment time. In addition, the source and drain regions can be formed thick so that their bottom surfaces are in contact with the SOI isolation insulating film 102, and a semiconductor device with small parasitic capacitance and high operation speed can be obtained.

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a view for explaining a semiconductor device according to one embodiment of the present invention, wherein FIG. 2 (a) is a plan view showing the structure of a MOSFET, and FIG. 2 (b) is FIG. 2 (a). 13 is a sectional view taken along line BB ′ of FIG.

In the figure, 201 to 204 and 207 to 211 are the same as the semiconductor device shown in FIG. In this embodiment, the source and drain regions 205 and 206 have plane defects 212 extending from the surface in the thickness direction and perpendicular to the direction of the channel current at a position near the channel region and a position away from the channel region. The surface defect portion is configured to be in contact with the insulating underlayer.

Needless to say, the source and drain regions 205 and 206 are made of a single crystal semiconductor. This is because a surface defect 212 exists in a part of the source and drain regions 205 and 206.
Is present because both sides of the plane defect 212 must have a crystal structure without crystal defects, that is, a single crystal structure.

 Next, the operation and effect will be described.

In this embodiment having such a configuration, the source / drain regions 20 formed in the semiconductor layer 204 on the SOI isolation insulating film 202 are formed.
5,206 has a structure having a surface defect 212 extending from the surface in the thickness direction, so that the impurity introduced into the semiconductor layer 204 diffuses to a deeper position in the surface defect portion than in other portions. Become. That is, as is apparent from FIG. 2B, the source region 205 and the drain region 206 are each formed in a single crystallized portion of the single crystal semiconductor layer 204,
A first impurity diffusion region having a side surface in contact with the channel region and a bottom surface separated by a predetermined distance from the surface of the SOI isolation insulating film 102; and a single impurity diffusion region located on a side opposite to the channel region from the first impurity diffusion region. A structure having a second impurity diffusion region in contact with the surface of the SOI isolation insulating film 202 at a position of a crystal defect region 212 consisting of a plane defect perpendicular to the direction of a channel current flowing in the channel region of the crystal semiconductor layer 104 Is what it is. Therefore, even when the semiconductor layer 204 on the SOI isolation insulating film 202 is thick, without increasing the ion implantation energy at the time of impurity introduction and the heat treatment time for impurity diffusion,
The source and drain regions 205 and 206 can be partially formed in contact with the surface of the insulating base layer 202 below the single crystal semiconductor layer, thereby making it possible to prevent damage due to ion implantation and leakage of impurities to the channel region. Without the above problems, it is possible to reduce the junction capacitance at the bottom of the source and drain regions.

Further, as described above, in the grain boundary diffusion, since the diffusion rate of impurities is high, even when it is desired to shorten the heat treatment time, such as when forming a structure in which element formation regions are stacked in a three-dimensional element, A semiconductor device with small parasitic capacitance in an element formation region can be easily manufactured.

Further, when the crystal defect is anisotropic as in the case of the above-mentioned plane defect, the diffusion in the lateral direction can be suppressed, and the diffusion can be performed only in the depth direction. Furthermore, the shape of the junction can be suppressed, and junctions having different depths can be simultaneously formed by ion implantation of the source and drain once.

In addition, since the surface defect 212 extending in the thickness direction from the surface of the source and drain regions is formed at a position near the channel region so as to be perpendicular to the direction of the channel current,
The semiconductor layer 204 below the source / drain regions has the surface defect 2
As a result, the junction capacitance is substantially divided by the twelve portions, and the junction capacitance that substantially serves as a parasitic capacitance can be greatly reduced. In other words, the portion of the semiconductor layer 204 separated by the surface defect 212 near the channel region on the side opposite to the channel region is electrically separated from the channel region, so that this portion is bonded to the source / drain regions 205 and 206. The capacitance does not act as a parasitic capacitance, and there is an effect that the junction capacitance acting as the parasitic capacitance can be reduced to only the junction capacitance with the source / drain regions in the channel region side portion of the partitioned semiconductor layer.

Further, since the source and drain regions 205 and 206 are composed of a single crystal semiconductor layer, they have better crystallinity than those composed of a polycrystalline semiconductor layer, and can reduce resistance and obtain good device characteristics. Further, since the crystallinity of the source and drain regions is good, the surface morphology is good, and the contact portion between the wiring layer and the source and drain regions can have low contact resistance and high structural reliability.

In the above embodiment, the case where the surface defect is formed in the direction perpendicular to the direction of the channel current (the direction of the electric field), that is, in the direction perpendicular to the lateral direction of the paper surface of FIG. May be a plane parallel to the direction of the channel current. In this case, the junction capacitance is reduced particularly when the bias voltage is high. This is because, when the bias voltage is increased, the depletion layer extends from the PN junction at the bottom of the source and drain regions to the SOI isolation insulating film 202, thereby causing the semiconductor layer 204 below the source and drain regions to be substantially insulative. This is because it becomes an area.

Further, in the above embodiment, the case where the surface defect reaches the SOI isolation insulating film 202 is shown, but the surface defect does not have to reach the SOI isolation insulating film 202, and in this case, the bias voltage is high. In this state, the junction capacitance is reduced by depleting the semiconductor layer below the bottom of the source and drain regions.

〔The invention's effect〕

In the case where the MOS transistor is formed in the single crystal semiconductor layer formed on the insulating base layer as described above, each of the source region and the drain region of the MOS transistor is in contact with the channel region of the single crystal semiconductor layer. And a first impurity diffusion region having a bottom surface separated by a predetermined distance from the surface of the insulating base layer, and a first impurity diffusion region located on a side opposite to the channel region from the first impurity diffusion region and having a crystal defect region of the single crystal semiconductor layer. Since the semiconductor device has the second impurity diffusion region in contact with the surface of the insulating base layer at the position, the impurity introduction is performed when the thickness of the single crystal semiconductor layer formed in contact with the surface of the insulating base layer is large. Part of the source and drain regions reach the insulating underlayer below the single crystal semiconductor layer without increasing the ion implantation energy and the heat treatment time for impurity diffusion during the process. It can be formed as,
As a result, there is no problem in the manufacturing process, such as damage due to ion implantation and leakage of impurities into the channel region.
This has the effect of reducing the junction capacitance at the bottom of the drain region.

In addition, if the single crystal semiconductor layer has a plane defect perpendicular to the direction of the channel current flowing in the channel region of the single crystal semiconductor layer, the source region and the drain region each have a channel defect due to the crystal defect region. And a region on the opposite side thereof, and the junction capacitance which substantially acts as a parasitic capacitance can be greatly reduced. In other words, of this partitioned semiconductor layer,
Since the portion opposite to the channel region is electrically separated from the channel region, the junction capacitance between this portion and the source / drain region does not act as a parasitic capacitance, and the junction capacitance acting as a parasitic capacitance is partitioned as described above. This has the effect of reducing only the junction capacitance of the portion of the semiconductor layer on the channel region side with the source and drain regions.

[Brief description of the drawings]

FIG. 1 is a view for explaining the basic principle of the present invention. FIG. 1 (a) is a plan view, and FIG. 1 (b) is a view A of FIG. 1 (a).
It is -A 'sectional drawing. FIG. 2 is a view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 (a) is a plan view, and FIG.
FIG. 2B is a sectional view taken along the line BB 'of FIG. 2A. Third
3A and 3B are views showing a conventional semiconductor device. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along the line CC 'of FIG. 3A. 101 is a silicon substrate, 102 is an SOI isolation insulating film, 103 is an element isolation insulating film, 104 is a P-type semiconductor layer, 105 and 106 are source and drain regions, 107 is a gate electrode, 110-1 and 11
0-2 and 110-3 are contact holes, and 112 is a crystal defect. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A first region which is formed on a surface of an insulating base layer made of an insulating material and is in contact with the surface and serves as a channel region, and sandwiches the first region. A first-conductivity-type single-crystal semiconductor layer having second and third regions each having a crystal defect region extending to the first and second regions.
A first impurity diffusion region formed by introducing impurities of the second conductivity type from the surface side and having a side surface in contact with the channel region and a bottom surface separated by a predetermined distance from the surface of the insulating underlayer; A source region and a drain region which are located on the opposite side of the channel region from the first impurity diffusion region and have a second impurity diffusion region in contact with the surface of the insulating base layer at the position of the crystal defect region; A gate electrode formed via a gate insulating film on a channel region of the single crystal semiconductor layer sandwiched between a side surface of the first impurity diffusion region of the region and a side surface of the first impurity diffusion region of the drain region A semiconductor device comprising: 2. A first region formed on a surface of an insulating base layer made of an insulating material and in contact with the surface and serving as a channel region, and each of the first region is sandwiched between the first region and a thickness direction. A first-conductivity-type single-crystal semiconductor layer having a second and a third region having a crystal defect region near the channel region, the crystal defect region including a plane defect perpendicular to the direction of the channel current flowing in the channel region, In each of the second and third regions of the single crystal semiconductor layer,
A first impurity diffusion region formed by introducing impurities of the second conductivity type from the surface side and having a side surface in contact with the channel region and a bottom surface separated by a predetermined distance from the surface of the insulating underlayer; A source region and a drain region which are located on the opposite side of the channel region from the first impurity diffusion region and have a second impurity diffusion region in contact with the surface of the insulating base layer at the position of the crystal defect region; A gate electrode formed via a gate insulating film on a channel region of the single crystal semiconductor layer sandwiched between a side surface of the first impurity diffusion region of the region and a side surface of the first impurity diffusion region of the drain region A semiconductor device comprising: