JPS62296563A - Insulated-gate transistor and manufacture thereof - Google Patents
Insulated-gate transistor and manufacture thereofInfo
- Publication number
- JPS62296563A JPS62296563A JP14082986A JP14082986A JPS62296563A JP S62296563 A JPS62296563 A JP S62296563A JP 14082986 A JP14082986 A JP 14082986A JP 14082986 A JP14082986 A JP 14082986A JP S62296563 A JPS62296563 A JP S62296563A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin
- transistor
- recrystallized
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 239000010408 film Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000001953 recrystallisation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
産業上の利用分野
本発明は、Ｓ ＯＩ （５ｉｌｉｃｏｎ Ｏｎ Ｉｎ５
ｕｌａｔｏｒ）構造（７） 絶縁ゲート型トランジスタ
および、その製造方法に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Application Field The present invention is directed to SOI (5ilicon On In5
ulator) Structure (7) This relates to an insulated gate transistor and its manufacturing method.
従来の技術
近年、ＳＯ工槽構造ＭＯＳ）ランジスタは、ソース、ド
レインがＳｉ基板から絶縁分離されているだめ、α線や
光に強いなどの多くの特長があり非常に注目を集めるよ
うになってきた。Conventional technology In recent years, SO transistors (MOS) transistors have attracted a lot of attention due to their many features, such as their source and drain being insulated and separated from the Si substrate, and their resistance to alpha rays and light. Ta.
以下、図面を参照しながら、上述したような従来のＳＯ
ＩＯ造の半導体装置について説明する。Hereinafter, with reference to the drawings, the conventional SO
An IO semiconductor device will be explained.
第３図は従来の半導体装置の断面構造を示すものである
。第３図において、１はＳｉ 基板、２は絶縁膜、３
は再結晶化したＳｉ薄膜でその膜厚は５０００人程度で
ある。さらに、４はＳｉ 薄膜３上に形成したゲート酸
化膜、６はゲート電極、６はソース、７はドレインから
なる構成となっている０
発明が解決しようとする問題点
しかしながら、上記のような構成では、ゲート酸化膜４
の下のチャネル部にα線や光が入射すると、電子とホー
ルが発生し、電子はドレインに移動し、ホールはソース
に移動して、トランジスタのリーク電流となる。FIG. 3 shows a cross-sectional structure of a conventional semiconductor device. In FIG. 3, 1 is a Si substrate, 2 is an insulating film, and 3
is a recrystallized Si thin film with a thickness of about 5,000 layers. Further, 4 is a gate oxide film formed on the Si thin film 3, 6 is a gate electrode, 6 is a source, and 7 is a drain. Problems to be Solved by the Invention However, the above structure Now, gate oxide film 4
When alpha rays or light enter the channel below the transistor, electrons and holes are generated, the electrons move to the drain, and the holes move to the source, resulting in leakage current in the transistor.
本発明は上記欠点に鑑み、チャネル部で発生する電荷に
よるリーク電流を低減することができる絶縁ゲート型ト
ランジスタとその製造方法を提供するものである。In view of the above drawbacks, the present invention provides an insulated gate transistor and a method for manufacturing the same, which can reduce leakage current due to charges generated in the channel portion.
問題点を解決するだめの手段
上記問題点を解決するだめに、本発明の絶縁ゲート型ト
ランジスタは、再結晶化したＳｉ 薄膜の膜厚を２００
０八以下した構造になっている。その製造方法は、６０
００人のｐｏｌｙ、−３ｉを再結晶化した後、熱酸化に
よりＳｉ 表面を酸化して、さらにそのＳｉＯ２を除去
することから構成されている。Means for Solving the Problems In order to solve the above problems, the insulated gate transistor of the present invention has a recrystallized Si thin film with a thickness of 200 mm.
It has a structure that is less than 08. The manufacturing method is 60
The method consists of recrystallizing 0000 poly, -3i, oxidizing the Si surface by thermal oxidation, and further removing the SiO2.
作用
この構成によれば、薄膜トランジスタ（ＴＰＴ）のチャ
ネル部の膜厚が薄いだめ、α線や光によってチャネル部
で発生する電荷は低減され、トランジスタのリーク電流
を減少させることができる。According to this configuration, since the thickness of the channel portion of the thin film transistor (TPT) is small, the charge generated in the channel portion by α rays or light is reduced, and the leakage current of the transistor can be reduced.
したがって、α線や光に強いトランジスタが得られる。Therefore, a transistor that is resistant to α rays and light can be obtained.
実施例
以下、本発明の実施例について、図面を参照しながら説
明する。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.
第１図は、本発明の実施例における絶縁ゲート型トラン
ジスタの断面図である。FIG. 1 is a cross-sectional view of an insulated gate transistor according to an embodiment of the present invention.
第１図において、１はＳｉ 基板、２は絶縁膜、１３は
再結晶化した薄いＳｉ 薄膜で、その膜厚は２００八〜
２０００八程度である。さらに、Ｓｉ薄膜３上に形成し
た４はゲート酸化膜、５はゲート電極、６はソース、７
はドレインからなる構成になっている。In Fig. 1, 1 is a Si substrate, 2 is an insulating film, and 13 is a recrystallized thin Si thin film, the film thickness of which is 2008 ~
It is about 20008. Further, 4 formed on the Si thin film 3 is a gate oxide film, 5 is a gate electrode, 6 is a source, and 7 is a gate oxide film.
consists of a drain.
以上のように構成された本発明の絶縁ゲート型トランジ
スタは、再結晶化Ｓｉ 薄膜１３の膜厚が従来のものよ
り１１５程度と薄いため、α線や光によってチャネル部
８に発生する電荷は極めて少なくなす、トランジスタの
リーク電流は大きく減少する。In the insulated gate transistor of the present invention configured as described above, the thickness of the recrystallized Si thin film 13 is about 115 mm thinner than that of the conventional one, so that the charge generated in the channel part 8 by α rays or light is extremely small. The leakage current of the transistor is greatly reduced.
以下、本発明の絶縁ゲート型トランジスタの製造方法に
ついて第２図を用いて説明する。例えば、６へ−７
レーザ光、電子ビーム、ゾーンメルティングなどでポリ
シリコンを再結晶化するためには、Ｓｉ薄膜の膜厚が５
０００八程度必要である。もし、Ｓｉ薄膜が１００ｏ人
程度に薄いと、再結晶化する際にＳｉ の飛散が発生し
安定した再結晶化が行なえない。The method for manufacturing an insulated gate transistor of the present invention will be described below with reference to FIG. For example, to 6-7, in order to recrystallize polysilicon using laser light, electron beam, zone melting, etc., the thickness of the Si thin film must be 5
Approximately 0008 is required. If the Si thin film is as thin as about 100 degrees, Si 2 will scatter during recrystallization and stable recrystallization will not be possible.
そこで、本発明の絶縁ゲート型トランジスタの製造方法
では、絶縁膜２の上にＰｏ１ｙ Ｓｉを６０００人程変
成長し、第２図ａに示すようにその８ｉ薄膜を再結晶化
する。次に、第２図すに示すようにＳｉ 薄膜を、酸化
により、１０００八程度Ｓｉ が残るように表面を熱酸
化する。さらに、第２図Ｃに示すようにその熱酸化をエ
ツチングで除去して、絶縁膜２の上に薄い再結晶化Ｓｉ
薄膜１３を形成する。Therefore, in the method of manufacturing an insulated gate transistor of the present invention, approximately 6,000 layers of PolySi are grown on the insulating film 2, and the 8i thin film is recrystallized as shown in FIG. 2a. Next, as shown in FIG. 2, the surface of the Si thin film is thermally oxidized so that about 1000% Si remains. Furthermore, as shown in FIG.
A thin film 13 is formed.
その後は、第２図ｄに示すように従来のＭＯＳプロセス
で薄膜トランジスタを形成する。本製造方法は、再結晶
化プロセスと８ｉ薄膜膜厚制御が安定しているため、再
現性のすぐれた製造方法である。Thereafter, a thin film transistor is formed by a conventional MOS process as shown in FIG. 2d. This manufacturing method is a manufacturing method with excellent reproducibility because the recrystallization process and 8i thin film thickness control are stable.
６へ−７
また、本実施例では、ｎ−ｃｈＭＯ８）ランジスタを例
にして説明したが、ｐ−ｃｈＭＯ８）ランジスタとして
もよいことは言うまでもない。6 to 7 Further, in this embodiment, an n-ch MO8) transistor is used as an example, but it goes without saying that a p-ch MO8) transistor may also be used.
発明の効果
以上のように本発明によれば、再結晶化Ｓｉ 薄膜を２
０００Å以下に薄したことにより、α線や光に強い安定
した薄膜トランジスタを作ることができ、その実用的効
果は大なるものがある。Effects of the Invention As described above, according to the present invention, the recrystallized Si thin film is
By thinning the material to less than 1,000 Å, it is possible to create a stable thin film transistor that is resistant to alpha rays and light, and has great practical effects.
第１図は本発明の一実施例におけるＳＯＩ構造の絶縁ゲ
ート型トランジスタの断面図、第２図は本発明の一実施
例における絶縁ゲート型トランジスタの製造方法を示す
断面図、第３図は従来のＳＯＩ構造の絶縁ゲート型トラ
ンジスタの断面図である。
１・・・・・・Ｓｉ基板、２・・・・・・絶縁膜、３・
・・・・・再結晶化Ｓｉ、４・・・・・・ゲート酸化膜
、５・・・・・・ゲート電極、６．７・・・・・・ソー
ス・ドレイン、８・・・・・・チャネル部、１３・・・
・・・薄い再結晶化Ｓｉ薄膜。FIG. 1 is a cross-sectional view of an insulated gate transistor with an SOI structure according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing an insulated gate transistor according to an embodiment of the present invention, and FIG. 3 is a conventional 1 is a cross-sectional view of an insulated gate transistor having an SOI structure. 1... Si substrate, 2... Insulating film, 3...
...Recrystallized Si, 4...Gate oxide film, 5...Gate electrode, 6.7...Source/drain, 8...・Channel part, 13...
...Thin recrystallized Si thin film.
Claims (3)
Å以下の半導体薄膜中にソース領域、ドレイン領域、チ
ャンネル部が形成されていることを特徴とする絶縁ゲー
ト型トランジスタ。(1) Thickness 2000 mm provided on the substrate via an insulating film
An insulated gate transistor characterized in that a source region, a drain region, and a channel portion are formed in a semiconductor thin film with a thickness of Å or less.
徴とする特許請求の範囲第１項記載の絶縁ゲート型トラ
ンジスタ。(2) The insulated gate transistor according to claim 1, wherein the semiconductor thin film is recrystallized silicon.
工程と、前記ポリシリコンを再結晶化する工程と、前記
再結晶化したシリコンを２００Å〜２０００Åの厚さ残
るように表面を熱酸化する工程と、前記熱酸化膜を除去
する工程とを備えたことを特徴とする絶縁ゲート型トラ
ンジスタの製造方法。(3) A process of growing polysilicon on the insulating film on the substrate, a process of recrystallizing the polysilicon, and heating the surface so that the recrystallized silicon remains at a thickness of 200 Å to 2000 Å. A method for manufacturing an insulated gate transistor, comprising the steps of oxidizing and removing the thermal oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14082986A JPS62296563A (en) | 1986-06-17 | 1986-06-17 | Insulated-gate transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14082986A JPS62296563A (en) | 1986-06-17 | 1986-06-17 | Insulated-gate transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62296563A true JPS62296563A (en) | 1987-12-23 |
Family
ID=15277687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14082986A Pending JPS62296563A (en) | 1986-06-17 | 1986-06-17 | Insulated-gate transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62296563A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04147629A (en) * | 1990-10-09 | 1992-05-21 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US5116771A (en) * | 1989-03-20 | 1992-05-26 | Massachusetts Institute Of Technology | Thick contacts for ultra-thin silicon on insulator films |
| JPH04301623A (en) * | 1991-03-29 | 1992-10-26 | Sharp Corp | Production of thin-film transistor |
| JPH07162011A (en) * | 1993-10-26 | 1995-06-23 | Internatl Business Mach Corp <Ibm> | Method for forming circuit having radiation resistance |
-
1986
- 1986-06-17 JP JP14082986A patent/JPS62296563A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5116771A (en) * | 1989-03-20 | 1992-05-26 | Massachusetts Institute Of Technology | Thick contacts for ultra-thin silicon on insulator films |
| JPH04147629A (en) * | 1990-10-09 | 1992-05-21 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH04301623A (en) * | 1991-03-29 | 1992-10-26 | Sharp Corp | Production of thin-film transistor |
| JPH07162011A (en) * | 1993-10-26 | 1995-06-23 | Internatl Business Mach Corp <Ibm> | Method for forming circuit having radiation resistance |
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