JPS635559A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS635559A
JPS635559A JP14877586A JP14877586A JPS635559A JP S635559 A JPS635559 A JP S635559A JP 14877586 A JP14877586 A JP 14877586A JP 14877586 A JP14877586 A JP 14877586A JP S635559 A JPS635559 A JP S635559A
Authority
JP
Japan
Prior art keywords
fet
soi
silicon
film
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14877586A
Other languages
Japanese (ja)
Inventor
Koji Senda
耕司 千田
Eiji Fujii
英治 藤井
Yoshimitsu Hiroshima
広島 義光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP14877586A priority Critical patent/JPS635559A/en
Publication of JPS635559A publication Critical patent/JPS635559A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To enable formation of an SOI.FET and a single crystal FET at the same time on the same substrate by a method wherein the pattern of an LOCOS film is formed on the silicon substrate, a poly-silicon film is formed thereon, the poly-silicon film is recrystallized, and the recrystallized silicon film is removed excluding the part to be used as the active region of the SOI.FET. CONSTITUTION:The manufacturing process of the titled device is constructed of a process to form an LOCOS film 2 and channel stopper regions 3 on the surface of a silicon substrate 1, a process to form a poly-silicon film thereon and to recrystallize 4 the poly-silicon film thereof, a process to remove selectively the recrystallized silicon film 4 thereof according to etching, and a process to form an MOS.FET. Accordingly, are SOI (Silicon On Insulator) .FET and a single crystal FET can be formed at the same time on the same substrate l, and formation of a high speed circuit, etc. utilizing the SOI.FET can be attained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、S OI (Sillicon On In
5ulator)−FICTと単結晶FKTとを同時に
形成できる半導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to SOI (Silicon On In
This invention relates to a method for manufacturing a semiconductor device that can simultaneously form FICT and single crystal FKT.

従来の技術 近年、SO工溝構造MOS )ランジスタは、ソース・
ドレインがシリコン基板から絶縁分離されているため、
ソース・ドレインの寄生容量が小さく、α線や光に強い
など、多くの特長があり非常に注目を集めるようになっ
てきた。
Conventional technology In recent years, SO trench structure MOS) transistors have been
Because the drain is isolated from the silicon substrate,
It has attracted a lot of attention because of its many features, such as low parasitic capacitance in the source and drain, and resistance to alpha rays and light.

発明が解決しようとする問題点 しかしながら、従来の製造方法は、SOI・FKTだけ
を作る方法であって、SOI・FETと単結晶FITと
を同一基板上に形成するような製造方法はない。
Problems to be Solved by the Invention However, the conventional manufacturing method is a method for manufacturing only SOI/FKT, and there is no manufacturing method for forming SOI/FET and single crystal FIT on the same substrate.

本発明は、上記欠点に鑑み、同一基板上にSOI・FI
Tと単結晶FETとを同時に形成することができる半導
体装置の製造方法を提供するものである。
In view of the above drawbacks, the present invention provides SOI and FI on the same substrate.
The present invention provides a method for manufacturing a semiconductor device that can simultaneously form a T and a single crystal FET.

問題点を解決するための手段 上記問題点を解決するために、本発明の半導体装置の製
造方法は、シリコン基板の表面に、LOGO3膜とチャ
ネルストップ領域を形成する工程と、その上にポリシリ
コンを成膜し、そのポリシリコンを再結晶化する工程と
、その再結晶化シリコンを毛ツチングで選択的に除去す
る工程と、MOSFETを形成する工程とから構成され
る装る。
Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes a step of forming a LOGO3 film and a channel stop region on the surface of a silicon substrate, and a step of forming a polysilicon film on the surface of the silicon substrate. The process consists of a process of forming a polysilicon film and recrystallizing the polysilicon, a process of selectively removing the recrystallized silicon by hair cutting, and a process of forming a MOSFET.

作用 この構成によれば、同一基板上に同時1csOI・FI
Tと単結晶FITとを形成することができる。
Function: According to this configuration, 1csOI and FI can be simultaneously installed on the same substrate.
T and single crystal FIT can be formed.

そのため、SOX・FETを利用した高速回路などを作
ることが可能になる。
Therefore, it becomes possible to create high-speed circuits using SOX FETs.

実施例 以下、本発明の実施例について、図面を参照しながら説
明する。
EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

第1図〜第4図は、本発明の一実施例におけるSOI・
FETと単結晶FITとを同時に形成する半導体装置の
製造方法の工程断面図を示すものである。第1図におい
て、1はSi基板、2はSiO□からなるLOCO3膜
、3はチャネルストップ領域、4は再結晶化シリコン、
5はラテラル・シード・エピタキシー技術に必要なシー
ド領域、7は単結晶FIT、8は5OIFKTである。
FIG. 1 to FIG. 4 show SOI/FIG. 4 in one embodiment of the present invention.
1 is a process cross-sectional view of a method for manufacturing a semiconductor device in which an FET and a single-crystal FIT are simultaneously formed. In FIG. 1, 1 is a Si substrate, 2 is a LOCO3 film made of SiO□, 3 is a channel stop region, 4 is recrystallized silicon,
5 is a seed region necessary for the lateral seed epitaxy technique, 7 is a single crystal FIT, and 8 is a 5OIFKT.

以下、本実施例の工程を説明する。第1図に示すように
1従来のLOGO5工程によシ、LOGO32パタンに
より、トランジスタ領域6とシード領域5を形成し、さ
らに、L、0CO817)SiO□2膜の下にはp+の
チャネルストップ領域3を形成する。L000S膜のS
iO2の膜厚ば、次の工程の再結晶化が安定してできる
ように、300o入〜60oO人が適切である。
The steps of this example will be explained below. As shown in FIG. 1, according to the conventional LOGO5 process, a transistor region 6 and a seed region 5 are formed according to the LOGO32 pattern, and a p+ channel stop region is further formed under the L,0CO817)SiO□2 film. form 3. S of L000S film
The appropriate thickness of the iO2 film is 300° to 60° so that recrystallization in the next step can be performed stably.

次に1第2図に示すように、ポリシリコンを3ooo八
〜5000Aの膜厚で成膜する。その後、例えばレーザ
ビームや電子ビームによυ、ポリシリコンを溶融して再
結晶化シリコン4膜を作る。その時、シード領域5を利
用したラテラル・シード・エピタキシー技術によりLO
GO3膜2上にも、結晶性のすぐれた再結晶化シリコン
4が得られる。
Next, as shown in FIG. 2, a polysilicon film is formed to a thickness of 3000 to 5000 Å. Thereafter, the polysilicon is melted using, for example, a laser beam or an electron beam to form four recrystallized silicon films. At that time, LO
Recrystallized silicon 4 with excellent crystallinity can also be obtained on the GO3 film 2.

次に、第3図に示すように、ホトリソグラフィーを利用
してSOI・FX’I’を作る領域だけ、再結晶化シリ
コン4を残して、それ以外の領域は、シリコンのドライ
エッチ工程により除去する。
Next, as shown in Figure 3, the recrystallized silicon 4 is left only in the area where SOI/FX'I' will be formed using photolithography, and the other areas are removed by a silicon dry etching process. do.

次に、従来のnチャネルMO3FETを作るプロセスで
、ゲート電極、ソース・ドレインなどを作れば、第4図
に示すように、単結晶FET7とSOI・FET8が同
時に作成できる。
Next, by making the gate electrode, source/drain, etc. in the process of making a conventional n-channel MO3FET, a single crystal FET 7 and an SOI FET 8 can be made at the same time, as shown in FIG.

また、本実施例では、nチャネルMoSトランジスタを
例にして説明したが、pチャネルMOSトランジスタと
してもよいことは言うまでもないことである。
Further, in this embodiment, an n-channel MoS transistor is used as an example, but it goes without saying that a p-channel MOS transistor may also be used.

発明の効果 以上のように本発明により、SOI・FITと単結晶F
ICTとを同時に形成できるため、その実用的効果は大
なるものがある。
Effects of the Invention As described above, the present invention enables SOI/FIT and single crystal F
Since ICT and ICT can be formed at the same time, the practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第4図は、本発明の一実施例における半導体装
置の製造方法の工程断面図である。 1・・・・・・Si基板、2・・・・・・LOGO5膜
、3・・・・・・チャネルストップ領域、4・・・・・
・再結晶化シリコン、5・・・・・・シード領域、6・
・・・・・トランジスタ領域、7・・・・・・単結晶M
O3)ランジスタ、8・・・・・・SOrMOSトラン
ジスタ。
1 to 4 are process cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1...Si substrate, 2...LOGO5 film, 3...channel stop region, 4...
・Recrystallized silicon, 5... Seed region, 6.
...Transistor region, 7...Single crystal M
O3) transistor, 8...SOrMOS transistor.

Claims (1)

【特許請求の範囲】[Claims] シリコン基板上にLOCOS膜のパターンを形成する工
程と、前記シリコン基板上にポリシリコンを形成し、前
記ポリシリコンを再結晶化する工程と、再結晶化したシ
リコンをSOI・FETの活性領域となる部分を除き除
去する工程と、前記シリコン基板上にMOS・FETを
形成する工程とを備えていることを特徴とする半導体装
置の製造方法。
A step of forming a LOCOS film pattern on a silicon substrate, a step of forming polysilicon on the silicon substrate and recrystallizing the polysilicon, and the recrystallized silicon becomes an active region of an SOI/FET. A method for manufacturing a semiconductor device, comprising the steps of: removing a portion of the silicon substrate; and forming a MOS/FET on the silicon substrate.
JP14877586A 1986-06-25 1986-06-25 Manufacture of semiconductor device Pending JPS635559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14877586A JPS635559A (en) 1986-06-25 1986-06-25 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14877586A JPS635559A (en) 1986-06-25 1986-06-25 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS635559A true JPS635559A (en) 1988-01-11

Family

ID=15460384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14877586A Pending JPS635559A (en) 1986-06-25 1986-06-25 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS635559A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252398A (en) * 1993-02-25 1994-09-09 Nec Corp Thin film integrated circuit and fabrication of the same
US5721444A (en) * 1994-12-22 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Thin-film transistor having a buried impurity region and method of fabricating the same
JP2008505488A (en) * 2004-06-30 2008-02-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Technology for forming substrates having crystalline semiconductor regions with different characteristics

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214381A (en) * 1975-07-25 1977-02-03 Hitachi Ltd Mis-type semiconductor device
JPS5667923A (en) * 1979-11-07 1981-06-08 Toshiba Corp Preparation method of semiconductor system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5214381A (en) * 1975-07-25 1977-02-03 Hitachi Ltd Mis-type semiconductor device
JPS5667923A (en) * 1979-11-07 1981-06-08 Toshiba Corp Preparation method of semiconductor system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252398A (en) * 1993-02-25 1994-09-09 Nec Corp Thin film integrated circuit and fabrication of the same
US5721444A (en) * 1994-12-22 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Thin-film transistor having a buried impurity region and method of fabricating the same
JP2008505488A (en) * 2004-06-30 2008-02-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Technology for forming substrates having crystalline semiconductor regions with different characteristics

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