JPS6336010B2 - - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit for arbitrarily changing the bit order from the least significant bit to the most significant bit of a parallel digital signal.

BACKGROUND OF THE INVENTION Digital pattern generators output parallel digital signals through multiple probe chips. If you make a mistake in the connection order when connecting the probe chips to the circuit under test, simply reconnect them correctly. However, when there are a large number of probe chips or many probe chips are connected in a narrow area, it is difficult to find the incorrectly connected probe chip, and it is difficult to connect the incorrectly connected probe tip. There was a risk that a properly connected probe tip could be pinched or removed when reconnecting. Therefore, a change circuit is installed inside the pattern generator to change the order of the probe chips.
That is, the bit order of the parallel digital signals is changed.

One of the pattern generation methods of a pattern generator is
The created parallel digital patterns are stored in memory, and this memory is sequentially read out. Therefore, in the conventional bit order changing circuit, when storing a created parallel digital pattern in a memory, the bit order of the pattern is changed in advance by software. However, when the count output of the counter is a parallel digital pattern, the bit order of the count output cannot be changed by software, so this conventional bit order changing circuit cannot be used.

Other conventional bit order changing circuits, when the parallel digital pattern is N bits (N: an integer of 2 or more), provide N multiplexers with N input terminals, supply parallel digital signals to all the multiplexers, and , each multiplexer selected one of the N input terminals in response to the control circuit. However, as the number of bits in the parallel digital signal increases, the number of multiplexers increases in this conventional bit order changing circuit, resulting in a large and complicated configuration.

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a bit order changing circuit for parallel digital signals that can change the bit order of parallel digital signals with a simple configuration without changing the bit order in advance.

SUMMARY OF THE INVENTION The bit reordering circuit for parallel digital signals of the present invention includes a random access memory having address terminals and data terminals, and a pattern writing circuit. This pattern writing circuit is composed of a read-only memory, a counter, and a control circuit. The read-only memory has an address terminal and a data terminal connected to the data terminal of the random access memory, and stores a plurality of patterns corresponding to changes in bit order. Further, the output terminal of the counter is connected to the lower bit address terminal of the read-only memory and the address terminal of the random access memory. The control circuit is
Bit reordering information for selecting a desired one of a plurality of patterns is supplied to the address terminal of the upper bit of the read-only memory, controlling counting of the counter, and writing and reading of the random access memory. Control.

When changing the bit order of parallel digital signals,
The control circuit places the random access memory in a write mode, causes the counter to start counting, and provides bit reordering information to the read-only memory to write the desired one of the plurality of patterns to the read-only memory. Random access by reading from
store in memory. Then, with the random access memory in read mode, parallel digital signals are provided to the address terminals of the random access memory, and parallel digital signals with changed bit order are obtained from the data terminals of the random access memory. .

Embodiments of the Invention Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. A 4-bit parallel digital signal is provided via terminals 10-16 and latch circuit 20 to address terminals A0-A3 of memory 22. Latch circuit 20 is, for example, a D-type flip-flop, and receives a clock signal synchronized with the parallel digital signal via terminal 18 to compensate for skew between bits of the parallel digital signal. The memory 22 is a random access memory (RAM), and has address terminals A0 to A3 and data input terminals D0' to
A signal from the pattern writing circuit 24 is received at D3' and the write/read control terminal W/R. RAM
22 data output terminals D0 to D3 to terminals 26 to 3
Connect to 2.

In this embodiment, since the parallel digital signal has 4 bits, there are 24 combinations of bit orders. Using each combination as one pattern, the pattern writing circuit 24 writes a pattern in the RAM 22 according to the change in the bit order of the parallel digital signal. A block diagram of an example of this pattern writing circuit 24 is shown in FIG. Read-only memory (ROM)
34 stores 24 patterns, and the lower 4 bits A0 to A3 of address terminals A0 to A8 are
Receives the output of the 4-bit counter 36. Each address position of each pattern is designated by the address signal of the lower 4 bits. The upper five bits of the address terminal of the ROM 34 receive information regarding a change in bit order from the control circuit 38, and select one of 24 patterns. Data terminals D0-D3 of the ROM 34 and output terminals A0-D3 of the counter 36
A3 is the data input terminal D0'~D of RAM22
3' and address terminals A0 to A3, respectively.
Further, the control circuit 38 controls the counting of the counter 36 and also controls writing and reading of the RAM 22.

When exchanging the first and fourth bits (signals at terminals 10 and 16) of the parallel digital signal and exchanging the second and third bits (signals at terminals 12 and 14), the control circuit of the pattern writing circuit 24 38
sets RAM22 to write mode, and
The pattern shown in FIG. 3 is selected from the ROM 34. The counter 36 sequentially advances the addresses of the RAM 22 and ROM 34 from "0000" to "1111".
Data corresponding to each address from ROM34
Transfer to RAM22. Therefore, the pattern shown in FIG. 3 is written into the RAM 22. After this writing is completed, the RAM 22 enters the read mode. This pattern is address A0 and data D3.
However, address A1 and data D2 are address A2
It should be noted that the address A3 and the data D1 are the same, and the address A3 and the data D0 are the same.

Parallel digital signal is D-type flip-flop 2
address terminals A0 to A3 of RAM22 through
data corresponding to each address is output to output terminals 26-32. For example, when the parallel digital signal is "0011", the data at address "0011" is "1100", so the parallel digital signals at terminals 26 to 32 are "1100". Similarly, if the input parallel digital signal is "1010", the output digital signal will be "0101". In this way, the first and fourth bits and the second and third bits of the input parallel digital signal are changed.

If there is no need to change the bit order of the parallel digital signal, a pattern in which addresses A0 to A3 are equal to data D0 to D3, respectively, is written in the RAM 22. Further, in a pattern where the bit order is changed to the order of the fourth bit, the first bit, the third bit, and the second bit, addresses A0, A1, A2, and A3 are equal to data D3, D0, D2, and D1, respectively. That is, each pattern assigns each bit value of D0 to D3 to address A0 according to the bit order to be changed.
It is sufficient to set the bit value to be equal to the bit value of ~A3. In addition,
The number of address and data terminals of RAM 22 must be equal to the number of bits of the parallel digital signal.

The address is 8 bits and the data is 4 bits.
If RAM is used as shown in the embodiment of FIG. 1, the number of bits of the parallel digital signal is limited to 4 bits. An embodiment not subject to this restriction will be described with reference to FIG. In this example, the bus is shown as a straight line with the number of bits added to the RAM 22 with 8-bit addresses and 4-bit data.
-1 and 22-2 are connected in parallel. That is, the 8-bit parallel digital signal is applied via a D-type flip-flop (latch circuit) 20 to address terminals A0 to A7 of RAMs 22-1 and 22-2. The pattern writing circuit 24 commonly supplies an 8-bit address signal to the address terminals A0 to A7 of the RAMs 22-1 and 22-2, and also supplies the upper 4 bits and lower 4 bits of the 8-bit data signal, respectively.
Data input terminal D of RAM22-1 and 22-2
0' to D3'. RAM22-1 and 22
A parallel digital signal with a changed bit order is generated at the -2 data output terminals D0 to D3. RAM
22-1 contains a pattern related to the upper 4 bits of the bit order to be changed, that is, addresses A0 to A7.
Four patterns corresponding to data D0 to D3 are written in a desired order. Also RAM22-
A pattern relating to the lower four bits of the bit order to be changed, ie, a pattern in which the remaining four of addresses A0 to A7 correspond to data D0 to D3 in the desired order, is written in 2. Other operations are the same as those in the embodiment shown in FIG. 1, so explanations will be omitted.

Effects of the Invention As described above, according to the present invention, there is no need to change the bit order of the parallel digital signal using software in advance, so even if the parallel digital signal is the counting output of a counter, the bit order can be changed freely. . Furthermore, the configuration is simple because the bit order can be changed by equivalently using an N-bit address and N-bit data memory without providing N N-input multiplexers for each bit of the N-bit parallel digital signal. Furthermore, the bit order can be freely selected by changing the contents of the memory. Further, the pattern writing circuit includes a ROM, a counter, and a control circuit, and the ROM stores in advance a plurality of patterns regarding changes in bit order. Therefore, it is not necessary to create a new pattern to be stored in the RAM each time according to a desired change in the bit order, so the RAM pattern can be changed quickly. At this time, the count signal of the counter can be commonly used as the address signal of the ROM and RAM, which further simplifies the configuration.

Modifications to the Embodiments Although the above is a description of preferred embodiments of the invention, those skilled in the art will appreciate that various modifications can be made without departing from the spirit of the invention. For example, in the above example, the parallel digital signals are 4 bits and 8 bits.
However, the number of bits is arbitrary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first preferred embodiment of the present invention, FIG. 2 is a block diagram showing a pattern writing circuit used in the invention, and FIG. 3 is an example of a pattern generated by the pattern writing circuit. The pattern diagram, FIG. 4, is a block diagram of a second preferred embodiment of the present invention. 22, 22-1, 22-2: Random access memory, 34: Read-only memory, 3
6: Counter, 38: Control circuit.

Claims (1)

[Scope of Claims] 1. A random access memory having an address terminal and a data terminal;
A read-only memory having a data terminal connected to a data terminal of an access memory and storing a plurality of patterns according to changes in bit order; an address terminal of lower bits of the read-only memory; A counter whose output terminal is connected to the address terminal of the random access memory, and bit order change information for selecting a desired one of the plurality of patterns described above to the address terminal of the upper bit of the read-only memory. and a control circuit for controlling the count of the counter and for controlling the writing and reading of the random access memory, when changing the bit order of the parallel digital signal,
The control circuit places the random access memory in a write mode, causes the counter to start counting, and supplies the bit reordering information to the read-only memory to write a desired one of the plurality of patterns. is read from the read-only memory and stored in the random access memory, the random access memory is placed in a read mode, and the parallel digital signal is supplied to the address terminal of the random access memory. A bit order changing circuit for parallel digital signals, characterized in that a parallel digital signal whose bit order has been changed is obtained from the data terminal of the random access memory.