JPS59195740A - Bit order changing circuit for parallel digital signal - Google Patents

Abstract

PURPOSE:To change the bit order with a simple constitution by changing the bit order with a written pattern and outputting a changed parallel digital signal from the data output terminal of a memory. CONSTITUTION:24 kinds of pattern are stored in an ROM34, and the output of a 4-bit counter 36 is received by lower 4-bit A0-A3 out of address terminals A0- A8. The address position of each pattern is designated by an address signal of these lower 4-bit. Upper 5-bit of address terminals of the ROM34 receive information related to the change of the bit order from a control circuit 38 to select one of 24 kinds of pattern. Data terminals D0-D3 of the ROM34 and output terminals A0-A3 of the counter 36 are connected to data input terminals D0'-D3' and address terminals A0-A3 of an RAM22. The control circuit 38 controls not only counting of the counter 36 but also read and write of the RAM22.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit for arbitrarily changing the bit order from the least significant bit to the most significant bit of a parallel digital signal.

BACKGROUND OF THE INVENTION Digital pattern generators output parallel digital signals through multiple probe tips. If you make a mistake in the connection order when connecting the probe tips to the circuit under test, you can simply reconnect them correctly. However, the probe
When there are a large number of tips or when there are many probes in a narrow area.
If the tips are connected, it is difficult to find the incorrectly connected probe tip, and when reconnecting the incorrectly connected probe tip, the correctly connected probe tip may be caught or removed. There was a risk. Therefore, a change circuit is installed inside the pattern generator,
The probe tip order, ie the bit order of the parallel digital signals, is changed.

One of the pattern generation methods of a pattern generator is to store created parallel digital patterns in a memory, and to read this memory sequentially. Therefore, when a conventional bit order changing circuit stores a created parallel digital pattern in a memory, the bit order of this pattern is changed in advance by software. However, when the counting output of the counter is a parallel digital pattern, the bit order of the counting output cannot be changed by software, so this conventional bit order changing circuit cannot be used.

In another conventional bit order changing circuit, when the parallel digital signal is N bits (N: an integer of 2 or more), N multiplexers each having N input terminals are provided, and parallel digital signals are supplied to all the multiplexers, and Depending on the control circuit, each multiplexer selected one of the N input terminals.

However, as the number of bits of the parallel digital signal increases, the number of multiplexers increases in this conventional bit order changing circuit, making the configuration large and complicated.

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a bit order changing circuit for parallel digital signals that can change the bit order of parallel digital signals with a simple configuration without changing the bit order in advance.

Summary of the Invention According to the pit order changing circuit for parallel digital signals of the present invention, there is provided a memory that has an address terminal and a data output terminal and can be freely written and read, and a pattern that corresponds to changing the bit order of parallel digital signals. and a pattern writing circuit for writing the pattern into the memory. When a parallel digital signal is supplied to the address terminal of the memory, the written buttered bit order is changed, and the changed parallel digital signal is output from the data output terminal of the memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. A 4-bit parallel digital signal is sent to the address terminals AO-A of the memory 22 via the terminals 10 to 16 and the latch circuit 20.
Supply to 3.

The latch circuit 20 is, for example, a D-type flip-flop, and receives a clock signal synchronized with the parallel digital signal via the terminal 18 to compensate for the skiing between each bit of the parallel digital signal. The memory 22 is a random access memory (RAM) and has address terminals A o , A
3. Signals from the pattern writing circuit 24 are received at the data input terminals 1) o' to 3-D 3' and the write/read control terminal W/H. Data output terminals DO-D3 of RAM 22 are connected to terminals 26-32.

In this embodiment, since the parallel digital signal has 4 pits, there are 24 combinations of bit orders. The pattern writing circuit 24 treats each combination as one pattern, and changes the bit order of the parallel digital signal (=writes the corresponding pattern into R).
Write to AM22.

A block diagram of an example of this pattern writing circuit 24 is shown in FIG. Read only memory (ROM) 34 is 24
The street pattern is memorized, and the address terminals AO to A
The output of the 14-bit counter 36 is received at AO-A3. Each address position of each pattern is specified by the address signals of the lower four pits.

The upper 5 bits of the address terminal of ROM34 are the control circuit 3.
8, and selects one of 24 patterns. Data terminals Do and D3 of the ROM 34 and output terminals AO4- to A3 of the counter 36 are connected to data input terminals Do' to D3' and address terminals AO-A and AO-3 of the RAM 22, respectively. Further, the control circuit 38 controls the counting of the counter 36, and also controls the count of the RA
Controls writing and reading of M22.

The first and fourth bits (signals at terminals 10 and 16) of the parallel digital signal are exchanged, and the second and third bits (signals at terminals 10 and 16) are exchanged.
When exchanging signals at terminals 12 and 14), control circuit 38 of pattern write circuit 24 puts RAM 22 in write mode and selects from ROM 34 the pattern shown in FIG.

The counter 36 sequentially advances the addresses in the RAM 22 and ROM 34 from 10000'' to 11111'' and transfers the data corresponding to each address from the ROM 34 to the RAM 22. Therefore, the pattern shown in FIG. 3 is written into the RAM 22. After this writing is completed, the RAM 22 enters the read mode. In this pattern, address AO and data D3, address AI and data D2, address A2
It should be noted that the address A3 and the data D1 are the same, and the address A3 and the data DO are the same.

Since the parallel digital signals are applied to the address terminals AO to A3 of the RAM 22 via the D-type flip-flop 20,
Data corresponding to each address is output to output terminals 26-32. For example, if the parallel digital signal is "0011", the data at address "0O11" is [1,100j, so the parallel digital signal at terminals 26 to 32 is l'-1100
It becomes J.

Similarly, if the input parallel digital signal is 11 O10J,
The output digital signal becomes l'-0101j. In this way, the first and fourth bits and the second and third bits of the input parallel digital signal are changed.

If there is no need to change the pit order of the parallel digital signal, a pattern in which addresses AO to A3 are respectively equal to data Do to D3 is written in the RAM 22. The pattern for changing the pit order in the order of 4th bit, 1st pit, 3rd bit, and 2nd bit is as follows:
, A2 and A3 are data D3. Do, D2 and Dl
is equal to That is, for each pattern, each bit value of DO to D3 may be made equal to the bit value of address AO-A3 according to the pit order to be changed. Note that the number of address and data terminals of the RAM 22 must be equal to the number of bits of the parallel digital signal.

If a RAM with 8 bits of address and 4 bits of data is used as shown in the embodiment of FIG. 1, the number of bits of the parallel digital signal will be limited to 4 bits. An embodiment not subject to this restriction will be described with reference to FIG. In this example, the bus is shown as a straight line with the number of bits added, and an 8-bit address allows 4-bit data to be stored in RAM 2.
2-1 and 22-2 are connected in parallel. That is, the 8-bit parallel digital signal is applied to address terminals AO and A7 of RAMs 22-1 and 22-2 via a D-type flip-flop (latch circuit) 20. The pattern writing circuit 24 is 8
Bit address signals are shared between RAM22-1 and RAM22-1.
-2 address terminal Ao-A7 and (-18
The upper 4 bits and lower 4 bits of the bit data signal are connected to the data input terminals DO' to D of R7-AM22-1 and 22-2, respectively.
3'. At the data output terminals D O-D 3 i of the RAMs 22-1 and 22-2, two parallel digital signals with a changed bit order are generated. A pattern relating to the upper four bits of the pit order to be changed, that is, a pattern in which four of addresses AO to A7 correspond to data DO-D3 in the desired order is written into the RAM 22-1. Also R
A pattern related to the lower four bits of the pit order to be changed, that is, a pattern in which the remaining four bits of address AONA7 correspond to data Do to D3 in the desired order is written into AM22-2. Other operations are the same as those in the embodiment shown in FIG. 1, so explanations will be omitted.

Effects of the Invention As described above, according to the present invention, there is no need to change the bit order of the parallel digital signal using software in advance, so even if the parallel digital signal is the count output of a counter, the pit order can be changed freely. Also, without providing N multiplexers for each bit of an N-bit parallel digital signal, it is possible to convert an N-bit address to an N-bit address isometrically.
The configuration is simple because the pit order can be changed using data memory. Furthermore, the pit order can be freely selected by changing the contents of the memory.

Modifications to the Embodiments Although the foregoing is a description of preferred embodiments of the invention, those skilled in the art will appreciate that various modifications can be made without departing from the spirit of the invention.

For example, a microprocessor system may be used for the pattern writing circuit, and the pattern regarding the pit order may be created by software. Further, in the pattern writing circuit, the pit order of the parallel count output of the counter may be changed by the microprocessor system, and the changed count output may be used as a pattern related to the pit order. Further, in the above description, the parallel digital signals are 4 bits and 8 bits, but the number of bits is arbitrary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first preferred embodiment of the present invention, and FIG.
FIG. 3 is a block diagram showing an example of a pattern writing circuit used in the present invention, FIG. 3 is a pattern diagram showing an example of a pattern generated by the pattern writing circuit, and FIG.
FIG. 2 is a block diagram of an embodiment. 22.22-1.22-2: Memory 24: Pattern writing circuit Patent applicant: Sony Tektronix Co., Ltd.
M Figure 3

Claims (1)

[Claims] a memory having an address terminal and a data output terminal, and a pattern writing circuit that writes a pattern in the memory according to a change in the bit order of the parallel digital signal, and supplies the parallel digital signal to the address terminal of the memory. A bit order changing circuit for parallel digital signals, characterized in that a parallel digital signal whose bit order has been changed is obtained from the data output terminal of the memory.