JPS6335159U - - Google Patents

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Publication number
JPS6335159U
JPS6335159U JP12697586U JP12697586U JPS6335159U JP S6335159 U JPS6335159 U JP S6335159U JP 12697586 U JP12697586 U JP 12697586U JP 12697586 U JP12697586 U JP 12697586U JP S6335159 U JPS6335159 U JP S6335159U
Authority
JP
Japan
Prior art keywords
received data
data
computer system
transmitting
dual computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12697586U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12697586U priority Critical patent/JPS6335159U/ja
Publication of JPS6335159U publication Critical patent/JPS6335159U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す処理手順構成
図、第2図はデユアルコンピユータシステム間の
結合状態図、第3図は従来の処理手順構成図であ
る。 1,2……デユアルコンピユータ、3,3
,4,4……コンピユータ、5,5……
伝送路、6,6……リンク。
FIG. 1 is a block diagram of a processing procedure showing an embodiment of the present invention, FIG. 2 is a diagram of a connection state between dual computer systems, and FIG. 3 is a block diagram of a conventional processing procedure. 1, 2...Dual computer, 3 1 , 3 2
, 4 1 , 4 2 ... computer, 5 1 , 5 2 ...
Transmission line, 6 1 , 6 2 ... link.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デユアルコンピユータシステムと他のシステム
間のデータ伝送において、伝送路の一方の障害発
生時に受信データを取込むためのバツフアリング
手段と、該受信データのブロツク化手段と、該ブ
ロツク化した受信データをシステム内リンクを介
して他系に転送する手段と、該受信データの受領
確認送信手段とを夫々独立的に行う構成にしたこ
とを特徴とするデユアルコンピユータシステムの
受信処理装置。
In data transmission between a dual computer system and another system, there is provided a buffering means for taking in received data when a failure occurs on one of the transmission paths, a means for blocking the received data, and a means for converting the blocked received data into the system. 1. A reception processing device for a dual computer system, characterized in that means for transmitting data to another system via a link and means for transmitting receipt confirmation of the received data are independently performed.
JP12697586U 1986-08-20 1986-08-20 Pending JPS6335159U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12697586U JPS6335159U (en) 1986-08-20 1986-08-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12697586U JPS6335159U (en) 1986-08-20 1986-08-20

Publications (1)

Publication Number Publication Date
JPS6335159U true JPS6335159U (en) 1988-03-07

Family

ID=31021284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12697586U Pending JPS6335159U (en) 1986-08-20 1986-08-20

Country Status (1)

Country Link
JP (1) JPS6335159U (en)

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