JPH0455U - - Google Patents

Info

Publication number
JPH0455U
JPH0455U JP3849190U JP3849190U JPH0455U JP H0455 U JPH0455 U JP H0455U JP 3849190 U JP3849190 U JP 3849190U JP 3849190 U JP3849190 U JP 3849190U JP H0455 U JPH0455 U JP H0455U
Authority
JP
Japan
Prior art keywords
main
bus
sub
data
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3849190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3849190U priority Critical patent/JPH0455U/ja
Publication of JPH0455U publication Critical patent/JPH0455U/ja
Pending legal-status Critical Current

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Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例に係るデータ送受信
装置を備えたコンピユータ通信システムのブロツ
ク図、第2図aは実施例におけるデータ送信方式
を示すフローチヤート、第2図bは同実施例にお
けるデータ受信方式のフローチヤート、第3図は
従来例におけるデータ送信方式を示すフローチヤ
ートである。 5……シリアル通信線、7……メインCPU、
9……メインメモリ、11……サブCPU、12
……双方向RAM、13……シリアル通信インタ
フエイス。
FIG. 1 is a block diagram of a computer communication system equipped with a data transmitting/receiving device according to an embodiment of the present invention, FIG. 2a is a flowchart showing a data transmission method in the embodiment, and FIG. Flowchart of data reception method. FIG. 3 is a flowchart showing a data transmission method in a conventional example. 5... Serial communication line, 7... Main CPU,
9...Main memory, 11...Sub CPU, 12
...Bidirectional RAM, 13...Serial communication interface.

Claims (1)

【実用新案登録請求の範囲】 オペレーテイングシステムで作動されるメイン
中央処理装置及びメインバスを介してそれに接続
されるメインメモリを備えたメインコンピユータ
装置に付属されるデータ送受信装置であつて、 前記メインバスに対し並列配置されるサブバス
を有し、 前記メインバスと前記サブバスとの間に両バス
から入力されるデータを記憶すると共に両バスに
対して記憶データを出力できる双方向RAMを設
け、 前記サブバスに、他のコンピユータ装置との間
でデータ送受信する通信インタフエイスを設け、 前記サブバスに、前記メインバスから前期双方
向RAMに送られてきたデータを前記他のコンピ
ユータ装置に送信すると共に、他のコンピユータ
装置から前記双方向RAMに送られてきたデータ
を前記メインバスから前記メインメモリへ受信す
るよう前記メイン中央処理装置に指令するサブ中
央処理装置を備えたことを特徴とするデータ送受
信装置。
[Claims for Utility Model Registration] A data transmitting/receiving device attached to a main computer device comprising a main central processing unit operated by an operating system and a main memory connected thereto via a main bus, A bi-directional RAM is provided between the main bus and the sub-bus, which is capable of storing data input from both buses and outputting stored data to both buses; The sub-bus is provided with a communication interface for transmitting and receiving data with other computer devices, and the sub-bus is configured to transmit data sent from the main bus to the bidirectional RAM to the other computer device, and to transmit data sent from the main bus to the bidirectional RAM. A data transmitting/receiving device comprising a sub-central processing unit that instructs the main central processing unit to receive data sent from the computer device to the bidirectional RAM from the main bus to the main memory.
JP3849190U 1990-04-12 1990-04-12 Pending JPH0455U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3849190U JPH0455U (en) 1990-04-12 1990-04-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3849190U JPH0455U (en) 1990-04-12 1990-04-12

Publications (1)

Publication Number Publication Date
JPH0455U true JPH0455U (en) 1992-01-06

Family

ID=31546544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3849190U Pending JPH0455U (en) 1990-04-12 1990-04-12

Country Status (1)

Country Link
JP (1) JPH0455U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63255759A (en) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp Control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63255759A (en) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp Control system

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