JPH0434043U - - Google Patents
Info
- Publication number
- JPH0434043U JPH0434043U JP7494290U JP7494290U JPH0434043U JP H0434043 U JPH0434043 U JP H0434043U JP 7494290 U JP7494290 U JP 7494290U JP 7494290 U JP7494290 U JP 7494290U JP H0434043 U JPH0434043 U JP H0434043U
- Authority
- JP
- Japan
- Prior art keywords
- switch
- data
- fifo memory
- switches
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Computer And Data Communications (AREA)
- Small-Scale Networks (AREA)
Description
第１図は本考案を実施した通信コントローラを
表わす図、第２図は一般的な通信コントローラの
全体構成を表わす図、第３図及び第４図は従来の
通信コントローラの構成を表わす図である。
１……バス・インターフエイス、２……ＦＩＦ
Ｏメモリ、２１……第１のＦＩＦＯメモリ、２２
……第２のＦＩＦＯメモリ、３……シリアライザ
、４……デシリアライザ、ＳＷ１……第１のスイ
ツチ、ＳＷ２……第２のスイツチ、ＳＷ３……第
３のスイツチ。
FIG. 1 is a diagram showing a communication controller implementing the present invention, FIG. 2 is a diagram showing the overall configuration of a general communication controller, and FIGS. 3 and 4 are diagrams showing the configuration of a conventional communication controller. . 1...Bus interface, 2...FIF
O memory, 21...first FIFO memory, 22
...Second FIFO memory, 3...Serializer, 4...Deserializer, SW1...First switch, SW2...Second switch, SW3...Third switch.
Claims (1)
リと、内部で発生する送信データと外部からの受
信データとを切り替えて前記第１のＦＩＦＯメモ
リに与える第１のスイツチと、前記第１のＦＩＦ
Ｏメモリからのデータと外部からの受信データと
を切り替えて前記第２のＦＩＦＯメモリに与える
第２のスイツチと、前記第１のＦＩＦＯメモリか
らのデータと前記第２のＦＩＦＯメモリからのデ
ータとを切り替えて出力する第３のスイツチとを
備え、ループバツク時に、送信データを前記第１
のスイツチ、前記第１のＦＩＦＯメモリ、前記第
３のスイツチを経由して外部へ送信し、一旦送信
した前記送信データを前記第２のスイツチ、前記
第２のＦＩＦＯメモリを経由して内部に取り込む
ように前記第１、第２、第３のスイツチを制御す
ることを特徴とする通信コントローラ。 a first FIFO memory, a second FIFO memory, a first switch that switches between internally generated transmission data and externally received data and supplies it to the first FIFO memory;
a second switch that switches between data from the O memory and externally received data and supplies the data to the second FIFO memory; and a third switch for switching and outputting, and when loopback is performed, transmit data is sent to the first switch.
The data is transmitted to the outside via the switch, the first FIFO memory, and the third switch, and the transmitted data is taken into the device via the second switch and the second FIFO memory. A communication controller that controls the first, second, and third switches as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7494290U JPH0746991Y2 (en) | 1990-07-13 | 1990-07-13 | Communication controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7494290U JPH0746991Y2 (en) | 1990-07-13 | 1990-07-13 | Communication controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0434043U true JPH0434043U (en) | 1992-03-19 |
| JPH0746991Y2 JPH0746991Y2 (en) | 1995-10-25 |
Family
ID=31615082
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7494290U Expired - Lifetime JPH0746991Y2 (en) | 1990-07-13 | 1990-07-13 | Communication controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746991Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0752487A (en) * | 1993-08-12 | 1995-02-28 | Nec Corp | Ink ribbon cassette |
-
1990
- 1990-07-13 JP JP7494290U patent/JPH0746991Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0752487A (en) * | 1993-08-12 | 1995-02-28 | Nec Corp | Ink ribbon cassette |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0746991Y2 (en) | 1995-10-25 |
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