JPH0444047U - - Google Patents
Info
- Publication number
- JPH0444047U JPH0444047U JP8710590U JP8710590U JPH0444047U JP H0444047 U JPH0444047 U JP H0444047U JP 8710590 U JP8710590 U JP 8710590U JP 8710590 U JP8710590 U JP 8710590U JP H0444047 U JPH0444047 U JP H0444047U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- dma
- transfer device
- data transfer
- dma controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図は動作の一例を示すフローチヤート、
第３図は従来のデータ転送装置の構成ブロツク図
である。
１……ＣＰＵ、２……ＲＡＭ、３……ＤＭＡコ
ントローラ、４……バスアダプタフ、５……トラ
ンンシーバ／レシーバ、６……外部バス（ＧＰＩ
Ｂバス）、７……ＤＭＡコントローラ制御回路、
１０……システムバス、４０……論理回路。
FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing an example of operation,
FIG. 3 is a block diagram of a conventional data transfer device. 1... CPU, 2... RAM, 3... DMA controller, 4... Bus adapter, 5... Transceiver/receiver, 6... External bus (GPI
B bus), 7...DMA controller control circuit,
10...System bus, 40...Logic circuit.
Claims (1)
ＰＵと、ＲＡＭと、ＤＭＡコントローラと、前記
システムバスを規格化された外部バスに接続する
ためのバスアダプタとを備えたデータ転送装置に
おいて、 前記バスアダプタに、前記バスアダプタとＲＡ
Ｍとの間のデータ転送をＤＭＡ転送している状態
で、外部バス上の信号と内部ステートの状況によ
りＤＭＡ中止用の論理を生成し出力する論理手段
を設け、 前記ＤＭＡコントローラは、論理手段からのＤ
ＭＡ中止の信号を受け、ＤＭＡ停止を行いバス権
をＣＰＵに返すことを特徴とするデータ転送装置
。[Scope of claim for utility model registration] Cs connected to each other via a system bus
In a data transfer device comprising a PU, a RAM, a DMA controller, and a bus adapter for connecting the system bus to a standardized external bus, the bus adapter includes the bus adapter and the RA.
The DMA controller is provided with a logic means for generating and outputting logic for stopping the DMA based on the signal on the external bus and the state of the internal state while the data is being transferred to and from M using the DMA, D
A data transfer device characterized in that upon receiving an MA stop signal, the DMA is stopped and the bus right is returned to a CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8710590U JPH0444047U (en) | 1990-08-21 | 1990-08-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8710590U JPH0444047U (en) | 1990-08-21 | 1990-08-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444047U true JPH0444047U (en) | 1992-04-14 |
Family
ID=31819180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8710590U Pending JPH0444047U (en) | 1990-08-21 | 1990-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444047U (en) |
-
1990
- 1990-08-21 JP JP8710590U patent/JPH0444047U/ja active Pending
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