JPS63138743U - - Google Patents

Info

Publication number
JPS63138743U
JPS63138743U JP3171787U JP3171787U JPS63138743U JP S63138743 U JPS63138743 U JP S63138743U JP 3171787 U JP3171787 U JP 3171787U JP 3171787 U JP3171787 U JP 3171787U JP S63138743 U JPS63138743 U JP S63138743U
Authority
JP
Japan
Prior art keywords
lan
data
clock
terminal devices
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3171787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3171787U priority Critical patent/JPS63138743U/ja
Publication of JPS63138743U publication Critical patent/JPS63138743U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
  • Small-Scale Networks (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例におけるＬＡＮコン
トローラの構成図、第２図は本考案の一実施例に
おけるＬＡＮシステムの構成図、第３図は本考案
の一実施例における端末装置間の転送速度決定フ
ローチヤート、第４図は端末装置間の距離が大き
い場合の送信データ、および送信クロツクと受信
データ、および受信クロツクとの関係説明図であ
る。 １：バスケーブル、１１：バス・インタフエー
ス、１２：コマンドステータス・レジスタ、１３
：受信バツフア、１４：送信バツフア、１５：デ
ータリンク・コントローラ、１６：デコーダ、１
７：衝突検出回路、１８：エンコーダ、１９：ク
ロツクタイミング発生回路、２１〜２６：端末装
置、３１〜３６：ＬＡＮコントローラ、ａ１，ｂ
１：送信側データ有効マージン、ａ２，ｂ２：受
信側データ有効マージン、ＲＸＤ：受信データ、
ＴＸＤ：送信データ、ＲＸＣ：受信クロツク、Ｔ
ＸＤ：送信クロツク。 Fig. 1 is a block diagram of a LAN controller in an embodiment of the present invention, Fig. 2 is a block diagram of a LAN system in an embodiment of the present invention, and Fig. 3 is a diagram of transfer between terminal devices in an embodiment of the present invention. The speed determination flowchart in FIG. 4 is an explanatory diagram of the relationship between the transmission data, the transmission clock, the reception data, and the reception clock when the distance between the terminal devices is large. 1: Bus cable, 11: Bus interface, 12: Command status register, 13
: Receive buffer, 14: Transmit buffer, 15: Data link controller, 16: Decoder, 1
7: Collision detection circuit, 18: Encoder, 19: Clock timing generation circuit, 21 to 26: Terminal device, 31 to 36: LAN controller, a 1 , b
1 : Transmitting side data valid margin, a2 , b2 : Receiving side data valid margin, RXD: Received data,
TXD: Transmission data, RXC: Reception clock, T
XD: Transmission clock.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ＬＡＮ装置において、端末装置間のデータ転送
に先立ち、個々の端末装置毎に転送速度を任意に
設定するＬＡＮコントローラを備えたことを特徴
とするＬＡＮ装置。 1. A LAN device comprising a LAN controller that arbitrarily sets a transfer rate for each terminal device prior to data transfer between terminal devices.
JP3171787U 1987-03-04 1987-03-04 Pending JPS63138743U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171787U JPS63138743U (en) 1987-03-04 1987-03-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171787U JPS63138743U (en) 1987-03-04 1987-03-04

Publications (1)

Publication Number Publication Date
JPS63138743U true JPS63138743U (en) 1988-09-13

Family

ID=30837710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171787U Pending JPS63138743U (en) 1987-03-04 1987-03-04

Country Status (1)

Country Link
JP (1) JPS63138743U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03168899A (en) * 1989-11-29 1991-07-22 Nittan Co Ltd Monitor and control system and transmitting method
JPH03269750A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Bus diagnostic system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03168899A (en) * 1989-11-29 1991-07-22 Nittan Co Ltd Monitor and control system and transmitting method
JPH03269750A (en) * 1990-03-20 1991-12-02 Fujitsu Ltd Bus diagnostic system

Similar Documents

Publication Publication Date Title
JPS6453253A (en) External apparatus connected to digital data processing system
JPS63138743U (en)
JPH0564384B2 (en)
JPH047620B2 (en)
JPH0525001Y2 (en)
JPH062361Y2 (en) Balanced transmission device
JP3073830B2 (en) Communication control device
JPS6392956U (en)
JPH02143650U (en)
JP2501879B2 (en) Channel access method
JPH0238527Y2 (en)
JPS5826866B2 (en) Communication control device
JPS6432549A (en) Gateway
JPH0178448U (en)
JPH0535939B2 (en)
JPS63182932A (en) Data transfer error control system
JPS6266444U (en)
JPH0247953A (en) Data transfer system
JP2000174850A5 (en)
JPH0361389B2 (en)
JPS58195351U (en) Parallel bus simultaneous transfer device
JPS6123442A (en) Data processing system
JPH01159439U (en)
JPH0455U (en)
JPS59159059U (en) data transmission equipment