JPS58195351U - Parallel bus simultaneous transfer device - Google Patents
Parallel bus simultaneous transfer deviceInfo
- Publication number
- JPS58195351U JPS58195351U JP9305682U JP9305682U JPS58195351U JP S58195351 U JPS58195351 U JP S58195351U JP 9305682 U JP9305682 U JP 9305682U JP 9305682 U JP9305682 U JP 9305682U JP S58195351 U JPS58195351 U JP S58195351U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- indicates
- data transfer
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は１：１の計算板間結合の並列バス構成
図、第３図は双方向性論理バスの構成図、第４図は本考
案に於ける並列バス転送方式を具体化するリンケージ装
置のシーケンス、第５図は本考案の実施例を動作させた
時のタイムチャートである。
１０・・・受信データバッファ。Figures 1 and 2 are parallel bus configuration diagrams with 1:1 connection between calculation boards, Figure 3 is a configuration diagram of a bidirectional logic bus, and Figure 4 is a concrete diagram of the parallel bus transfer method in this invention. FIG. 5 is a time chart when the embodiment of the present invention is operated. 10... Receive data buffer.
Claims (1)
、双方の計算機から同時にデータ転送要求が発行された
時の回線衝突状態を検出する回路と、前記回線衝突の発
生を報告する信号回路及び、送信データ確立を意味する
ストローブ信号発生回路と、データを受信したことを示
すと共に受信側からの送信データ確立を示すアンサーバ
ック信号発生回路と、送信モード中に同時にデータ受信
を可能と子る受信データバッファ回路と、データ転送終
了を示すデータ転送終了信号発生回路を具備し、双方の
計算機から同時にデータ転送要求が発生した時に、遅く
データ転送要求を発行したと見えた側が回線衝突状態を
検出すると同時に、相手側リンケージ装置に報告し、そ
の信号の条件をもとに互いにデータ送信モードを保持し
、データ送信ストローブでデータを送受信し、且つ、前
記データ送信ストローブに対するアンサーバック信号で
も逆方向のデータ送受信を制御し送信モード中の受信デ
ータを格納するデータバッファ制御をすることにより、
半二重双方向性論理バスを全二重的制御で両方向同時転
送を可能とすることを特徴とする並列バス同時転送装置
。A circuit that detects a line collision state when data transfer requests are issued simultaneously from both computers in a bidirectional logical bus connection in a 1:1 connection between calculation boards, and a circuit that reports the occurrence of the line collision. A signal circuit, a strobe signal generation circuit that indicates the establishment of transmission data, and an answerback signal generation circuit that indicates that data has been received and also indicates the establishment of transmission data from the receiving side, and can simultaneously receive data during transmission mode. It is equipped with a secondary receive data buffer circuit and a data transfer end signal generation circuit that indicates the end of data transfer, and when data transfer requests are generated from both computers at the same time, the side that appears to have issued the data transfer request later is in a line collision state. At the same time as detecting a By controlling the data transmission and reception in the direction and controlling the data buffer that stores the received data in the transmission mode,
1. A parallel bus simultaneous transfer device, characterized in that it enables simultaneous transfer in both directions on a half-duplex bidirectional logical bus through full-duplex control.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9305682U JPS58195351U (en) | 1982-06-23 | 1982-06-23 | Parallel bus simultaneous transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9305682U JPS58195351U (en) | 1982-06-23 | 1982-06-23 | Parallel bus simultaneous transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58195351U true JPS58195351U (en) | 1983-12-26 |
Family
ID=30223632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9305682U Pending JPS58195351U (en) | 1982-06-23 | 1982-06-23 | Parallel bus simultaneous transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58195351U (en) |
-
1982
- 1982-06-23 JP JP9305682U patent/JPS58195351U/en active Pending
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