JPS6262364U

JPS6262364U -

Info

Publication number: JPS6262364U
Application number: JP15360985U
Authority: JP
Priority date: 1985-10-09
Filing date: 1985-10-09
Publication date: 1987-04-17

Description

[Brief explanation of the drawing]

第１図は、本考案の一実施例の入力装置と本体
側からくる信号を処理するキー入力ＣＥの回路構
成図、第２図は、入力装置を含む情報処理装置に
おける一般的な外観構成を示す斜視図、第３図は
第２図に示す構成を布線系よりみたブロツク図、
第４図は第３図に示す主制御回路の構成を示すブ
ロツク図、第５図は、入力装置起動側のときのタ
イミングを示すフオーマツト図、第６図は前記デ
ータ転送の時のシリアル転送を示すフオーマツト
図、第７図は入力装置と処理装置間のデータ送受
時間を観視するタイマＩＣの動作を示すタイミン
グ図、第８図、第９図は本考案の一実施例の処理
手順を示すフローチヤートである。３……入力装置、６……ケーブル、１６……キ
ー入力ＣＥ、３０……処理ＩＣ、３３……演算Ｌ
ＳＩ，１００，１０１……タイマＩＣ。 FIG. 1 is a circuit configuration diagram of an input device according to an embodiment of the present invention and a key input CE that processes signals coming from the main body side, and FIG. 2 is a general external configuration of an information processing device including the input device. FIG. 3 is a block diagram of the configuration shown in FIG. 2 viewed from the wiring system;
Fig. 4 is a block diagram showing the configuration of the main control circuit shown in Fig. 3, Fig. 5 is a format diagram showing the timing when the input device is activated, and Fig. 6 shows the serial transfer at the time of data transfer. 7 is a timing diagram showing the operation of a timer IC that monitors the data transmission and reception time between the input device and the processing device, and FIGS. 8 and 9 show the processing procedure of an embodiment of the present invention. It is a flowchart. 3...Input device, 6...Cable, 16...Key input CE, 30...Processing IC, 33...Calculation L
SI, 100, 101...Timer IC.

Claims

[Scope of utility model registration request]

In a signal transmission device between an input device having a plurality of contacts and a processing device that processes signals from the input device, at least three wires connect the two devices, and at least one of the wires connects the two devices. is used for signals and is configured to mutually send or receive signals on the signal line, the processing device has a first clock means for observing the time sent from the input device, The input device side has a second timer configured to be retriggerable by a signal on the signal line, and when the second timer reaches a set value, the main circuit of the input device is forcibly reset. , and the processing device side sends initial data to the input device side immediately after the setting of the first timer means is reached.