JPS59113830U

JPS59113830U - input device

Info

Publication number: JPS59113830U
Application number: JP480283U
Authority: JP
Inventors: 繁松岡
Original assignee: 株式会社日立製作所
Priority date: 1983-01-19
Filing date: 1983-01-19
Publication date: 1984-08-01

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は、入力装置の一般的な構成を示した斜視図、第
２図は、布線系よりみた構成図、第３図は主制御回路の
ブロック図、第４図は、本考案の一実施例の回路図、第
５図は、入力装置起動側のタイミングフォーマット図、
第６図はシリアル転送フォーマット図、第７図は、キー
ボードＣＥから入力装置へ送出されるデータ例示図、第
８、第９図は一実施例を示す処理フローチャート図であ
る。３・・・・・・入力装置、６・・・・・・ケーブル、１
０・・・・・＝ＣＰＵ、１６・・・・・・キーボードＣ
Ｅ、３Ｑ・・・・・・処理ＩＣ。３１・・・・・・バッファ素子、４５・・・・・・ワン
ショット回路、４６・・・・・・Ｄタイプフリップフロ
ップ、４７・・・・・・信号、４８・・・・・・制御信
号。茅Ａ　目一口］］１１丁Ｉ１１ルー、Ｊ７１　　　　　　　テ′−タ第　８１！］Figure 1 is a perspective view showing the general configuration of the input device, Figure 2 is a configuration diagram seen from the wiring system, Figure 3 is a block diagram of the main control circuit, and Figure 4 is a diagram of the present invention. The circuit diagram of one embodiment, FIG. 5, is a timing format diagram of the input device activation side.
FIG. 6 is a serial transfer format diagram, FIG. 7 is a diagram illustrating data sent from the keyboard CE to the input device, and FIGS. 8 and 9 are processing flowcharts showing one embodiment. 3...Input device, 6...Cable, 1
0...=CPU, 16...Keyboard C
E, 3Q... Processing IC. 31... Buffer element, 45... One shot circuit, 46... D type flip-flop, 47... Signal, 48... Control signal. Chia A Eye Bite]] 11th Street I1 1 Roux, J71 Te'-ta No. 81! ]

Claims

[Scope of utility model registration request]

Between an input device having a plurality of contacts and a processing device that processes signals from the input device,
In a device connected by a plurality of wires, at least one of which is used for a signal, and configured to mutually send or receive signals on the signal wire, an input device or a processing device is connected. 1. An input device comprising, within one of the devices, a circuit that manages the time from when data is transmitted until the data is transmitted from the other device.