JPS58117522U - pulse circuit - Google Patents

pulse circuit

Info

Publication number
JPS58117522U
JPS58117522U JP1141682U JP1141682U JPS58117522U JP S58117522 U JPS58117522 U JP S58117522U JP 1141682 U JP1141682 U JP 1141682U JP 1141682 U JP1141682 U JP 1141682U JP S58117522 U JPS58117522 U JP S58117522U
Authority
JP
Japan
Prior art keywords
pulse circuit
reset signal
signal generation
devices
microcomputers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1141682U
Other languages
Japanese (ja)
Inventor
洋 小沢
田中 泰成
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1141682U priority Critical patent/JPS58117522U/en
Publication of JPS58117522U publication Critical patent/JPS58117522U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案によるリセット信号供給方式を示す図、
第2図は本考案の一実施例を示す図、第3図は第2図の
4−n瞬時パルス遮断回路についての一実施例を示す図
である。 1−1〜1−n・・・マイクロコンピュータ、2・・・
リセット信号発生回路、3・・・リセット信号線、5・
・・電流制限用抵抗。
FIG. 1 is a diagram showing a reset signal supply method according to the present invention;
FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an embodiment of the 4-n instantaneous pulse cutoff circuit of FIG. 1-1 to 1-n...microcomputer, 2...
Reset signal generation circuit, 3... Reset signal line, 5.
...Resistance for current limiting.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロコンピュータを使用する装置を複数重するシス
テム装置において、該システム内の任意の構成装置のリ
セット信号発生回路からバスライ′  ン方式により、
他の構成装置に伝送することにより、システム内のリセ
ット信号発生回路を1つにしたことを特徴とするパルス
回路。
In a system device in which a plurality of devices using microcomputers are overlapped, the reset signal generation circuit of any constituent device in the system can be transmitted via a bus line method.
A pulse circuit characterized in that the number of reset signal generation circuits in a system is reduced to one by transmitting signals to other component devices.
JP1141682U 1982-02-01 1982-02-01 pulse circuit Pending JPS58117522U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1141682U JPS58117522U (en) 1982-02-01 1982-02-01 pulse circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1141682U JPS58117522U (en) 1982-02-01 1982-02-01 pulse circuit

Publications (1)

Publication Number Publication Date
JPS58117522U true JPS58117522U (en) 1983-08-11

Family

ID=30024024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1141682U Pending JPS58117522U (en) 1982-02-01 1982-02-01 pulse circuit

Country Status (1)

Country Link
JP (1) JPS58117522U (en)

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