JPH02143650U - - Google Patents
Info
- Publication number
- JPH02143650U JPH02143650U JP17155588U JP17155588U JPH02143650U JP H02143650 U JPH02143650 U JP H02143650U JP 17155588 U JP17155588 U JP 17155588U JP 17155588 U JP17155588 U JP 17155588U JP H02143650 U JPH02143650 U JP H02143650U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- signal line
- parallel data
- receiving device
- busy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims 3
- 238000012790 confirmation Methods 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Description
第１図はこの考案の一つの実施例に係るマルチ
マイクロコンピユーターシステムのブロツク図、
第２図乃至第４図は第１図中の第１のマイクロコ
ンピユータの動作を示すフローチヤート、第５図
乃至第７図は第１図中の第２のマイクロコンピユ
ータの動作を示すフローチヤート、第８図と第９
図は第１図のマルチマイクロコンピユータシステ
ムの動作を示すタイムチヤートである。第１０図
は従来のマルチマイクロコンピユータシステムの
ブロツク図である。
主な符号の説明、２０：第１のマイクロコンピ
ユータ、２２：第２のマイクロコンピユータ、２
４：データバス、２６：第１の周辺デバイス、２
８：第２の周辺デバイス。
FIG. 1 is a block diagram of a multi-microcomputer system according to one embodiment of this invention.
2 to 4 are flowcharts showing the operation of the first microcomputer in FIG. 1, and FIGS. 5 to 7 are flowcharts showing the operation of the second microcomputer in FIG. 1, Figures 8 and 9
The figure is a time chart showing the operation of the multi-microcomputer system of FIG. FIG. 10 is a block diagram of a conventional multi-microcomputer system. Explanation of main symbols, 20: first microcomputer, 22: second microcomputer, 2
4: data bus, 26: first peripheral device, 2
8: Second peripheral device.
Claims (1)
ータ送受信装置と、第１の並列データ送受信装置
と第２の並列データ送受信装置間に相互接続され
たデータバス及び第１の制御信号線と、第１の並
列データ送受信装置から第２の並列データ送受信
装置に向けて接続された第２の制御信号線と、第
２の並列データ送受信装置から第１の並列データ
送受信装置に向けて接続された第３の制御信号線
と、第１の並列データ送受信装置と第２の並列デ
ータ送受信装置間に相互接続されたデータバスに
接続された１または複数の周辺デバイスと、第１
の並列データ送受信装置及び（または）第２の並
列データ送受信装置から周辺デバイスに向けて接
続された周辺デバイス制御信号線と、 から成り、 第１の並列データ送受信装置と第２の並列デー
タ送受信装置の各々に、 第１の制御線がビジーかノツトビジーかを検出
する第１の検出手段と、 相手装置との間で転送を行うべきデータが発生
すると、第１の検出手段がノツトビジーを検出し
たあと第１の制御信号線をデータ転送が完了する
までビジーとし、かつ、第２の制御信号線を一時
的にアクテイブにして相手装置に対し転送指令を
行う転送指令手段と、 転送指令手段が転送指令を行つたあと、第２の
制御信号線と第３の制御信号線を用いてハンドシ
エイクしながら非同期確認方式により相手装置と
の間でデータの転送を行う第１のデータ転送手段
と、 自身の装置が第１の制御信号線をビジーとして
いないとき、第１の制御信号線と第２の制御信号
線を介して送られる相手装置からの転送指令を検
出する第２の検出手段と、 第２の検出手段が転送指令を検出したとき、第
２の制御信号線と第３の制御信号線でハンドシエ
イクしながら非同期確認方式により相手装置との
間でデータの転送を行う第２のデータ転送手段と
、 を備え、 第１の並列データ送受信装置及び（または）第
２の並列データ送受信装置に、 周辺デバイスとの間で転送を行うべきデータが
発生すると、第１の検出手段がノツトビジーを検
出したあと、第１の制御信号線をビジーにしてバ
スビジーであることを示すバスビジー指示手段と
、 バスビジー指示手段でバスビジーを指示した後
、周辺デバイス制御信号線で所定の転送制御を行
いながら周辺デバイスとの間でデータの転送を行
う周辺デバイス用データ転送手段と、 を備えたことを特徴とする並列データの送受信シ
ステム。[Claims for Utility Model Registration] A first parallel data transmitting/receiving device, a second parallel data transmitting/receiving device, a data bus interconnected between the first parallel data transmitting/receiving device and the second parallel data transmitting/receiving device, and A first control signal line, a second control signal line connected from the first parallel data transmitting/receiving device to the second parallel data transmitting/receiving device, and a first parallel data transmitting/receiving device connected from the second parallel data transmitting/receiving device. a third control signal line connected to the transmitting/receiving device; and one or more peripheral devices connected to a data bus interconnected between the first parallel data transmitting/receiving device and the second parallel data transmitting/receiving device. , 1st
a parallel data transmitter/receiver and/or a peripheral device control signal line connected from the second parallel data transmitter/receiver to the peripheral device, the first parallel data transmitter/receiver and the second parallel data transmitter/receiver When data to be transferred between the first control line and the other device is generated, the first detection means detects whether the first control line is busy or not busy. Transfer command means keeps a first control signal line busy until data transfer is completed and temporarily activates a second control signal line to issue a transfer command to a destination device; a first data transfer means that transfers data to and from the other device using an asynchronous confirmation method while handshaking using a second control signal line and a third control signal line; a second detection means for detecting a transfer command sent from the partner device via the first control signal line and the second control signal line when the first control signal line is not busy; a second data transfer unit that transfers data to and from the other device using an asynchronous confirmation method while handshaking on a second control signal line and a third control signal line when the detection unit detects the transfer command; When data to be transferred between peripheral devices is generated in the first parallel data transmitting/receiving device and/or the second parallel data transmitting/receiving device, after the first detecting means detects not busy, a bus busy instruction means that indicates that the bus is busy by making the first control signal line busy; A parallel data transmission/reception system comprising: a data transfer means for a peripheral device that transfers data;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17155588U JPH02143650U (en) | 1988-12-31 | 1988-12-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17155588U JPH02143650U (en) | 1988-12-31 | 1988-12-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02143650U true JPH02143650U (en) | 1990-12-05 |
Family
ID=31699744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17155588U Pending JPH02143650U (en) | 1988-12-31 | 1988-12-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02143650U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52112246A (en) * | 1976-03-18 | 1977-09-20 | Panafacom Ltd | Data processor |
| JPS57212519A (en) * | 1981-06-25 | 1982-12-27 | Mitsubishi Electric Corp | Programmable controller |
| JPS5924363A (en) * | 1982-07-31 | 1984-02-08 | Nec Home Electronics Ltd | Common connecting system of bus for plural microcomputers |
-
1988
- 1988-12-31 JP JP17155588U patent/JPH02143650U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52112246A (en) * | 1976-03-18 | 1977-09-20 | Panafacom Ltd | Data processor |
| JPS57212519A (en) * | 1981-06-25 | 1982-12-27 | Mitsubishi Electric Corp | Programmable controller |
| JPS5924363A (en) * | 1982-07-31 | 1984-02-08 | Nec Home Electronics Ltd | Common connecting system of bus for plural microcomputers |
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