JPH0178448U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining the operating state of the data bus terminal device according to this invention, Fig. 2 is a diagram showing a general serial data bus system, and Fig. 3 is a diagram of command signals in a general data bus system. FIG. 4 is a diagram showing an example of a data signal, FIG. 5 is a diagram showing an example of a status signal, FIG. 6 is a diagram showing a general data bus terminal device, and FIG. 7 is a diagram showing an example of a status signal. FIG. 2 is a diagram showing the operating state of a conventional data bus terminal device. In the figure, 1 is a serial data bus, 2 is a data bus terminal device of a control station, 3 is a data bus terminal device of a controlled station, 4 is a synchronization code, 5 is a controlled station terminal address code, 6 is a transmission/reception code, 7 is a sub address code, 8 is a word number code, 9 is a parity, 10 is a data word, 11 is a status word, 12 is a control section, 13 is a transmission register, 14 is an encoder, 15 is a driver, 16
is a receiver, 17 is a decoder, and 18 is a receiving register. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] In a data bus terminal device that transfers data with other devices via a serial data bus line,
What is claimed is: 1. A data bus terminal device, characterized in that it is configured to be able to simultaneously receive a signal transmitted by the own terminal device onto a serial data bus line during execution of data transfer.