JPS6331158A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To miniaturize a cell in its area, reduce changes in performance at working temperatures, and realize high-speed operations by a method wherein a load resistor, built of a mixture of precious metal and a high-melting metal oxide, high in layer resistance, and low in temperature coefficient, is provided in a memory cell. CONSTITUTION:A cermet film 11A, built of gold and a tantalum oxide and attached by spattering to an insulating film 10 coating the surface of a substrate, is patterned by dry etching. An oxide film 12 is formed by vapor growth on the cermet film 11A and serves as a protective film. A process follows wherein contact holes are provided on both ends of the resultant cermet resistor pattern, a titanium-tungsten alloy film 14 is attached to serve as a barrier film, an aluminum film 15 is attached to serve as an electrode metal, and an electrode wiring pattern is formed by dry etching. Here, the cermet film 11A is built of gold (Au) and a tantalum oxide (Ta2O5), which realizes a layer resistance high in value and low in thermal coefficient, and the resistance value may be controlled by changing the thickness and pattern of the cermet film 11A.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory device that is highly integrated and capable of high-speed operation, and particularly to a high-load semiconductor memory device that exhibits an extremely stable resistance value within a small cell area over the operating temperature range. This invention relates to the structure of a resistive element.

[Traditional martial arts]

Conventionally, a load resistor configured in a memory cell has been formed by adding impurities at a sufficiently low concentration to a polycrystalline silicon film.

FIG. 3 is a cross-sectional view of the load resistance part in the memory and cell of a conventional semiconductor memory device, and the resistance film is about 3,000 yen.
A large polycrystalline silicon film 11B doped with boron at a dose of about I x 10 "c!!L-" at 3QKev is used, and a platinum silicide film formed in a self-aligned manner is used in the contact area. 13 is formed. In addition, in FIG. 3, 1Ort insulating film, 12 a surface protection film, 14r
It is a titanium-tungsten alloy film and a 15ri aluminum model.

[Problem that the invention seeks to solve]

The load resistance of the conventional polycrystalline silicon film mentioned above changes greatly when the manufacturing conditions, especially the amount of impurities added, changes slightly, and the degree of this changes rapidly when the layer resistance exceeds IOKΩ10. The disadvantage was that it increased. Furthermore, the high resistance of the polycrystalline silicon film has an extremely large temperature coefficient, which has been a major constraint in designing a semiconductor device circuit with high-speed performance and stable characteristics.

An object of the present invention is to provide a semiconductor memory device that is equipped with a layer resistance having an extremely high resistance value and an extremely low temperature coefficient, achieves a small cell area, and is capable of high-speed operation with extremely little variation in characteristics within the operating temperature range. It is in.

[Means for solving problems]

The semiconductor memory device of the present invention has a load resistance in a memory cell that is made of a mixture of oxides of a noble metal and a refractory metal and has a high layer resistance and a small temperature coefficient.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. As shown in FIG. 1, a cermet film made of gold and tantalum oxides having a thickness of approximately 1000 AOI was deposited on the insulating film 10 provided on the surface of the substrate by dry etching. A vapor-phase grown oxide film 12 having a thickness of about 2000λ is deposited thereon as a surface protective film. After this, contacts are opened at both ends of the cermet resistor pattern, and then a titanium-tungsten alloy film as a barrier film is deposited using the sputtering method, and an aluminum film as a temporary electrode metal is deposited using the sputtering method with a thickness of approximately 1 μm. . After this, an embodiment of the present invention is completed by forming a stain mark line pattern by dry etching.

Temperature coefficient ≦-xooppm/'O at K n / o, ~
A layer resistance with a high resistance and a small temperature coefficient can be obtained with a temperature coefficient of ≦-300p pm/''O at a temperature coefficient of 100Ω and 10Ω.On the other hand, with the conventionally used polycrystalline silicon resistor, a temperature coefficient of +3000 or more can be obtained at a temperature coefficient of 10 to 10Ω. 5000ppm/
It is undesirable because it shows a value of 0 or more. Therefore, with polycrystalline silicon, it is not easy to obtain a layer resistance of several 10 to 10 or more, which is a problem.

In addition, as a mixture of oxides of other noble metals and high melting point metals, jjAu wo, system (~100 with Ω10~-xoo
oppm/”c), Pt-WO5 system (~100Ω10
~-2 sooppm/”c), Pt-Ta205 series (
~1OOKQ/mouth ~-2300 ppm/"O), etc. can be used similarly.

Note that the resistance value can be controlled by the cermet film thickness and pattern.

FIG. 2 is a longitudinal cross-sectional view of another embodiment of the present invention, in which a layer resistance υ made of a mixture of noble metal and high-melting point metal oxides is used as in the embodiment of FIG. 1, but the barrier gX14 The difference is that platinum silicide 13 is deposited and buttered before being deposited.

〔Effect of the invention〕

As explained above, the present invention uses a so-called cermet resistor, which is a mixture of oxides of noble metals and high-melting point metals, as a load resistor in semiconductor memory cells, so a layer resistance with high resistance and a small temperature coefficient can be obtained. As a result, a small cell area can be achieved.

Moreover, it is possible to obtain a semiconductor memory device capable of high-speed operation with extremely little variation in characteristics within the operating temperature range.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of one embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of another embodiment of the present invention, and FIG. 3 is a vertical cross-sectional view of an example of a conventional semiconductor memory device. 10... Insulating film, IIA... Length-met film, 11B... Polycrystalline silicon film, 12-...
...Surface protective film, 13...Platinum silicide film, 14...-Titanium-tungsten alloy film, 15
...Alzunium film.

Claims (1)

[Claims] A semiconductor memory device characterized in that a memory cell has a load resistance made of a mixture of oxides of a noble metal and a high-melting point metal, which has a high layer resistance and a small temperature coefficient.