JPS59161857A - Semiconductor device wiring and resistor therefor - Google Patents
Semiconductor device wiring and resistor thereforInfo
- Publication number
- JPS59161857A JPS59161857A JP58035814A JP3581483A JPS59161857A JP S59161857 A JPS59161857 A JP S59161857A JP 58035814 A JP58035814 A JP 58035814A JP 3581483 A JP3581483 A JP 3581483A JP S59161857 A JPS59161857 A JP S59161857A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- resistor
- forming
- resistance
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000002844 melting Methods 0.000 claims abstract description 5
- 239000012212 insulator Substances 0.000 claims abstract 3
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 238000010894 electron beam technology Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- -1 silicon ions Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は絶縁物に金属をイオン打込することによシ得ら
れる配線に係シ、特に高抵抗で微細配線でかつ平坦な配
線を必要とする半導体装置に好適δ１１゜
な半導体装置用配置抗体を提供する場合に極めて効を奏
するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to wiring obtained by ion-implanting metal into an insulating material, and particularly relates to wiring that requires high resistance, fine wiring, and flat wiring. This is extremely effective when providing a semiconductor device placement antibody having a suitable angle of δ11° for a semiconductor device.
従来、コンプリメンタリＭＯ８（Ｃ−ＭＯＳ ）を用い
たスタテイクーランダムアクセスメモリ（Ｓ−ＲＡＭ）
の集積密度の向上は主に、加工精度の向上と、負荷に多
結晶シリコンの高抵抗体を使用することによるメモリセ
ルの改良によっていた。しかしながら５−ＲＡＭがさら
に高密度、高集積化されるにしたがい配線幅が１〜２ミ
クロンメートルと細く要求されるようになシ、多結晶シ
リコンの微細加工が難かしくなってきた。また、微細化
が進むにつれて電極配線の断線を防ぐため、素子を構成
している各層の平坦化が必要になってきた。Conventionally, static random access memory (S-RAM) using complementary MO8 (C-MOS)
The increase in integration density was mainly due to improved processing accuracy and improved memory cells by using high resistance polycrystalline silicon as the load. However, as 5-RAMs become more dense and highly integrated, the wiring width is required to be as narrow as 1 to 2 micrometers, making it difficult to microfabricate polycrystalline silicon. Furthermore, as miniaturization progresses, it has become necessary to planarize each layer constituting the device in order to prevent disconnection of electrode wiring.
そして微細化が進むにつれて、高負荷抵抗体の長さ方向
の寸法は２〜４ミクロ程度に短かくなってきた。この程
度になると第１図の従来装置に示すように高抵抗多結晶
シリコン３につながる低抵抗多結晶シリコン配線４を形
成するために、９ん不純物５を拡散する工程で、りんが
高抵抗多結晶シリコン領域まで拡散してしまい、十分高
い高抵また、化学気相成長法やスパッタ法で得られる多
結晶シリコンの抵抗率は１×１０５〜ｌＸｌ０”Ω−ｍ
程度である。したがって微細化が進むと多結晶シリコン
を高抵抗体として用いることが難かしくなるという問題
があった。As miniaturization progresses, the lengthwise dimension of the high-load resistor has become shorter to about 2 to 4 microns. At this level, as shown in the conventional device shown in FIG. The resistivity of polycrystalline silicon obtained by chemical vapor deposition or sputtering is 1×105 to 1×10”Ω-m.
That's about it. Therefore, as miniaturization progresses, it becomes difficult to use polycrystalline silicon as a high-resistance material.
本発明の目的は、シリコン酸化膜あるいはシリコン窒化
膜に金属あるいはシリコンを直接イオン打込することに
より、上記の多結晶シリコンのような欠点の無い平坦で
かつ任意の抵抗を持つ微細抵抗あるいは配線を提供する
ことにある。An object of the present invention is to directly implant metal or silicon ions into a silicon oxide film or a silicon nitride film to create a flat microresistance or wiring having any resistance without the drawbacks of polycrystalline silicon. It is about providing.
上記目的を達成するための本発明の構成は、絶縁物上の
所定の位置にイオン打込み法で高融点金属あるいはシリ
コンをイオン打込みして上記絶縁物を局所的に配線ある
いは抵抗体として用いることにある。In order to achieve the above object, the present invention has a structure in which high-melting point metal or silicon is ion-implanted into a predetermined position on an insulating material using an ion implantation method, and the above-mentioned insulating material is used locally as a wiring or a resistor. be.
本発明に至った背景を述べてみると、従来、シリコ／酸
化膜やシリコン窒化膜を形成する過程で微量の金属不純
物を含有しているとこれらの絶縁膜の絶縁性が悪くなる
。本発明は上述の様にこれら不純物金属をイオン打込法
によシ制御性良く混入させることによシ任意の抵抗を持
つ酸化膜あるいは窒化膜を得るようにしたものである。To explain the background to the present invention, conventionally, when a silicon/oxide film or a silicon nitride film contains a trace amount of metal impurity in the process of forming the film, the insulation properties of these films deteriorate. In the present invention, as described above, an oxide film or a nitride film having a desired resistance can be obtained by mixing these impurity metals with good controllability by ion implantation.
このイオン打込に際し、打込金属の酸化物、窒化物の生
成エネルギよシリコ／酸化膜
成エネルギのほうが低くなる金属を適宜選ぶことが肝要
である。During this ion implantation, it is important to appropriately select a metal whose energy for forming silico/oxide film is lower than the energy for forming oxides and nitrides of the implanted metal.
本発明に適用される金属としてはＷ、Ｍｏ。Metals applicable to the present invention include W and Mo.
Ｔａ、Ｔｉなどの高融点金属であれば差違なく適用でき
同様の効果があるものであるが、打込んだ場合の欠陥低
減に付き、更に改良を加えることが望ましい。例えば、
チタンの酸化物はシリコン酸化物の生成エネルギより低
い。このため、チタンは熱処理工程によシリコ／酸化膜
を解離させ、局所的に低抵抗な欠陥部分を形成して抵抗
の制御ができなくなる場合がある。このような場合はさ
らに他のイオンを打込むことによシこのような欠陥の発
生を防ぐことができる。上記のチタンの場合はチタンと
窒素を同じ場所に打込むことによシ欠陥の発生を低減で
きる。以下実施例・を用いて詳細に説明する。High melting point metals such as Ta and Ti can be used without any difference and have similar effects, but it is desirable to make further improvements to reduce defects when implanted. for example,
The formation energy of titanium oxide is lower than that of silicon oxide. For this reason, titanium may cause the silicon/oxide film to dissociate during the heat treatment process, forming locally low-resistance defective portions, making it impossible to control the resistance. In such cases, the occurrence of such defects can be prevented by further implanting other ions. In the case of titanium, the occurrence of defects can be reduced by implanting titanium and nitrogen at the same location. A detailed explanation will be given below using Examples.
実施例１；
第２図は、本発明の一実施例としてＣ−ＭＯＳスタティ
ックメモリの負荷抵抗部分の概略断面図である。同図の
６の部分がメモリセルの高負荷抵抗部分である。高負荷
抵抗は以下の工程によシ作成した。素子間分離用酸化膜
を形成後、ネガ型の高耐熱性電子線レジスト７を用い電
子線ビーム露光により１ミクロンメートル幅で長さが４
ミクロンメートルのパターンを形成する。次に本実施例
ではシリコン、アルミニウム、チタンおよびタングステ
ン８をそｇそれ別々の試料に対し、メモリ作成工程終了
後で１０６Ωから１０１０Ωになるようにイオン打込し
た。その後、レジストを除去後、低圧気相成長法によシ
、多結晶シリコン３を堆積し、さらにυんを拡散する。Embodiment 1; FIG. 2 is a schematic sectional view of a load resistance portion of a C-MOS static memory as an embodiment of the present invention. The portion 6 in the figure is a high load resistance portion of the memory cell. The high load resistor was created using the following process. After forming an oxide film for isolation between elements, a negative type highly heat-resistant electron beam resist 7 is used to expose the film to a 1 micrometer wide and 4 mm long.
Forms micrometer patterns. Next, in this example, ions of silicon, aluminum, titanium, and tungsten 8 were implanted into separate samples so that the resistance ranged from 106Ω to 1010Ω after the memory fabrication process was completed. Thereafter, after removing the resist, polycrystalline silicon 3 is deposited by low pressure vapor phase epitaxy and further diffused.
次に電子線ビーム露によりパターンを形成後マイクロ波
プラズマエツチング法で多結晶シリコンを加工し配線と
した。Next, a pattern was formed by electron beam exposure, and then the polycrystalline silicon was processed by microwave plasma etching to form wiring.
多結晶シリコン配線とイオン打込領域の重なりは、１ミ
クロンメートルとした。したがって高抵抗部分の長さは
２ミクロンメートルである。The overlap between the polycrystalline silicon wiring and the ion implantation region was 1 micrometer. The length of the high resistance portion is therefore 2 micrometers.
実施例２；
本発明の他の実施例は第３図に示すように実施例１と同
様の素子構造であるが高抵抗領域を多結晶シリコン配線
３と上層のアルミニウム配線１０との接続部分の層間絶
縁膜９に実施例１と同様の金属をイオン打込することに
より形成した。Embodiment 2; As shown in FIG. 3, another embodiment of the present invention has the same device structure as Embodiment 1, but the high resistance region is connected to the polycrystalline silicon wiring 3 and the upper layer aluminum wiring 10. The interlayer insulating film 9 was formed by ion-implanting the same metal as in Example 1.
シん５を拡散した多結晶シリコン４を所定配線形状に加
工する。次に多結晶シリコンを酸化し約１００〜２００
ｎｍの層間酸化膜を形成する。続いて電子線ビーム露光
によ一リレシスト７に１ミクロン角の孔の開ける。次に
金属８をイオン打込した後レジストを除去した後アルミ
ニウム電極配線１０を形成する。このように負荷を多結
晶シリコン配線上に形成することによｐ高集積化が可能
になった。The polycrystalline silicon 4 in which the thin film 5 is diffused is processed into a predetermined wiring shape. Next, oxidize the polycrystalline silicon to approximately 100 to 200
An interlayer oxide film of nm thickness is formed. Next, a hole of 1 micron square is made in the resist 7 by electron beam exposure. Next, after ion implantation of metal 8 and removal of the resist, aluminum electrode wiring 10 is formed. By forming the load on the polycrystalline silicon wiring in this way, it has become possible to achieve high p-integration.
本発明によれば１ミクロン以下で１０６〜１０′。 According to the invention, it is less than 1 micron and 106 to 10'.
Ωの微細高抵抗を制御性良く得ることができるので１．
Ｃ−ＭＯＢスタテイクメモリの集積密度の向上に効果が
ある。1. It is possible to obtain a fine high resistance of Ω with good controllability.
This is effective in improving the integration density of C-MOB static memory.
一方、高濃度の金属イオン打込を行なうことにより、り
んを拡散した多結晶シリコンと同等あるいはそれ以下の
抵抗を持つ配線を得ることができる。したがって、この
配線を多結晶シリコン配線のかわりに用いることによシ
素子の平坦化微細化ができるため各種半導体装置の高集
積に対して効果がある。On the other hand, by implanting metal ions at a high concentration, it is possible to obtain wiring having a resistance equal to or lower than that of polycrystalline silicon in which phosphorus is diffused. Therefore, by using this wiring instead of polycrystalline silicon wiring, silicon elements can be planarized and miniaturized, which is effective for high integration of various semiconductor devices.
第１図は従来のＣ−ＭＯＳスタテイクメモリセルの高抵
抗部分の断面図、第２図および第３図は゛本発明の一実
施例としての高抵抗部分を微小化したメモリセル高抵抗
部分の断面図である。
１・・・シリコン基板、２・・・素子間分離用酸化膜、
３・・・高抵抗多結晶シリコン、４・・・低抵抗多結晶
シリコン、５・・・熱拡散したシん、６・・・金属イオ
ン打込した高抵抗体、７・・・レジスト、８・・・金属
イオン打込、９・・・層間絶縁膜、１０・・・アルミニ
ウム配線、１１・・・拡散層−
ＶＪ Ｉ 口
第２図
（α）
＋ φ φ φ ψ 會〜δ
Ｍ３ 図
（α）
１ ＋ Φ ψ φ 番〜８
（ｂ）
０FIG. 1 is a sectional view of a high-resistance portion of a conventional C-MOS static memory cell, and FIGS. 2 and 3 are sectional views of a high-resistance portion of a memory cell in which the high-resistance portion is miniaturized as an embodiment of the present invention. FIG. 1... Silicon substrate, 2... Oxide film for isolation between elements,
3...High resistance polycrystalline silicon, 4...Low resistance polycrystalline silicon, 5...Thermally diffused thin, 6...High resistance element implanted with metal ions, 7...Resist, 8 ...Metal ion implantation, 9...Interlayer insulating film, 10...Aluminum wiring, 11...Diffusion layer - VJ I Figure 2 (α) + φ φ φ ψ Society ~ δ M3 Figure ( α) 1 + Φ ψ φ number ~ 8 (b) 0
Claims (1)
るいはシリコンをイオン打込して配線あ２、特許請求の
範囲第１項において、上記金属は、イオン打込みに際し
ての打込み金属の絶縁化物の生成エネルギより半導体絶
縁化物の生成エネ1. Wiring by implanting high-melting point metal or silicon into predetermined positions on the insulator using the ion implantation method. 2. In claim 1, the metal is used to insulate the implanted metal during ion implantation. The energy for producing semiconductor insulators is greater than the energy for producing oxides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035814A JPS59161857A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device wiring and resistor therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58035814A JPS59161857A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device wiring and resistor therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59161857A true JPS59161857A (en) | 1984-09-12 |
Family
ID=12452393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58035814A Pending JPS59161857A (en) | 1983-03-07 | 1983-03-07 | Semiconductor device wiring and resistor therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59161857A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60120549A (en) * | 1983-12-02 | 1985-06-28 | Nippon Telegr & Teleph Corp <Ntt> | Resistor for semiconductor element |
| JPS6331158A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Semiconductor memory device |
| US4830976A (en) * | 1984-10-01 | 1989-05-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Integrated circuit resistor |
| US4965214A (en) * | 1987-07-31 | 1990-10-23 | Samsung Electronics Co., Ltd. | Method for manufacturing poly-crystal sillicon having high resistance |
| CN109637766A (en) * | 2018-12-21 | 2019-04-16 | 广州天极电子科技有限公司 | A kind of method of adjustment of tantalum nitride membrane resistor resistance value |
-
1983
- 1983-03-07 JP JP58035814A patent/JPS59161857A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60120549A (en) * | 1983-12-02 | 1985-06-28 | Nippon Telegr & Teleph Corp <Ntt> | Resistor for semiconductor element |
| US4830976A (en) * | 1984-10-01 | 1989-05-16 | American Telephone And Telegraph Company, At&T Bell Laboratories | Integrated circuit resistor |
| JPS6331158A (en) * | 1986-07-24 | 1988-02-09 | Nec Corp | Semiconductor memory device |
| US4965214A (en) * | 1987-07-31 | 1990-10-23 | Samsung Electronics Co., Ltd. | Method for manufacturing poly-crystal sillicon having high resistance |
| CN109637766A (en) * | 2018-12-21 | 2019-04-16 | 广州天极电子科技有限公司 | A kind of method of adjustment of tantalum nitride membrane resistor resistance value |
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