JPS63305527A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To relax the concentration of an electric field at the upper edge section of a groove, and to inhibit the generation of a kink phenomenon by forming a taper at the upper edge section of the groove, into which an insulating film is buried, in a semiconductor device in which the insulating film is buried in the groove shaped to the main surface of a semiconductor substrate and elements are isolated. CONSTITUTION:Grooves 121, 122 are formed vertically to the main surface of a semiconductor substrate 11, first insulating films 241, 242 are buried and shaped up to specified depth in the grooves, and regions in approximately 1000Angstrom or less in the upper edge sections of the grooves are isotropic-etched, and edges at the upper edge sections of the grooves are removed, thus shaping tapers 12a, 12d. The grooves are buried with second insulating films 251, 252 up to the main surface of the semiconductor substrate 11. According to such constitution, the concentration of an electric field at channel edge sections in the buried oxide films is removed. Accordingly, the generation of a kink phenomenon in sub-threshold region characteristics can be prevented, thus acquiring stable element characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device having a buried element isolation region and a method for manufacturing the same.

(Prior Art) Conventionally, when forming a fine buried type element isolation region, from the viewpoint of the degree of integration, the semiconductor substrate 11 is
Grooves 121 and 122 are formed perpendicularly to the main surface of the substrate, and these grooves 121 and 122 are filled with insulating films 131 and 132. In this FIG.
It shows a cross-sectional structure along the channel width direction of the FET, and although not shown, source and drain regions are formed in the surface area of the semiconductor substrate 11 between the insulating films 13, 132 at the front and back of the page, respectively. There is. And the channel formed between these source and drain regions! Iwj
, a gate electrode 15 is formed thereon with a gate insulating film 14 interposed therebetween.

However, in the above configuration, the element isolation region 13 . , 132 have a shape substantially perpendicular to the channel, the electric field is concentrated at the end of the channel, and the threshold voltage at this portion appears to be lower than that at the center of the upper channel.

For this reason, as shown in FIG. 5, in the gate voltage-channel current characteristics, in addition to the normal subthreshold characteristic (indicated by the broken line 16), the rA value voltage is low and the channel width is short (indicated by the solid line 17). ) is the width, and a kink ring 9 (area surrounded by a dashed line 18) occurs. Therefore, even if the threshold voltage is the same, the leakage current when the gate voltage is Ov is orders of magnitude larger. This means that, for example, a DRAM transfer gate has a MO with such characteristics.
When SFETs are used, this leads to the loss of stored information, which poses a major problem.

(Problems to be Solved by the Invention) As described above, a conventional semiconductor device having a buried element isolation region has a drawback in that a kink phenomenon occurs in subthreshold region characteristics, which adversely affects element characteristics.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a semiconductor device that can prevent the occurrence of the kink phenomenon in the subthreshold region characteristics and provide stable device characteristics, and its manufacture. The purpose is to provide a method.

(Means and effects for solving the problem) In other words, in this invention, in order to achieve the above object, a groove is formed perpendicularly to the main surface of a semiconductor substrate, and then a groove is formed in the groove to a predetermined depth. A first insulating film is buried and formed, and the #4 region of about 1000 Å or less at the upper end of this trench is isotropically etched to remove the edge at the upper end of the trench to form a taper. Then, the trench is filled up to the main surface of the semiconductor substrate with the second insulating film.

According to such a configuration, electric field concentration at the upper end of the groove can be alleviated, thereby suppressing the occurrence of the kink phenomenon, and providing good device characteristics.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, the same components as those in FIG.
a to 12d, and the grooves 12.a to 12d are formed. , 122, insulators [131, 13□] for element isolation are embedded.

Further, although not shown, in the surface area of the semiconductor substrate 110 between the insulators 111131 and 132, source and drain regions are formed at the front and back of the paper, respectively. A gate electrode 15 is formed on a channel region formed between these source and drain regions with a gate insulating film 14 interposed therebetween.

According to such a configuration, the buried oxide film 131°132
Since the electric field concentration at the chisenel edge portion is eliminated, the kink phenomenon in the subthreshold region of the MOS FET can be suppressed as shown in FIG. 3, and a buried type element isolation region with a small i can be formed.

2<a> to 2(d) sequentially show the manufacturing process of the semiconductor device shown in FIG. 1 above. First, as shown in FIG. 2(a), a thickness is 1000
After forming the thermal oxide film 19, a polysilicon film 20 with a thickness of 500 mm is formed on the thermal oxide film 19, #3 Jl: (
f N Sa 5000 people (7) CVD-8i 02 membrane 21
are sequentially deposited and formed. After that, apply photoresist 2 on the entire surface.
2 is coated, and a photolithography step and a subsequent RIE step are performed to form the CVD-8i 0211!21. Opening 23+ in polysilicon 1I20 and heat-aging film 19
, 232 are formed.

Next, perform RIE and test the semiconductor! After etching the main surface of the third layer 11 by approximately 8,000 etches to form grooves 121 and 122, the resist 22 was peeled off and CVD-8i etching was performed again.
02 N! The groove 12 is formed by depositing about 5,000 layers of I.
．． , 122 is embedded with this CVD-8t 0211a241°242. After that, CV D -S i 02 in the grooves 121 and 122! These CVD-8i 02 m24t, 242 were machined so that the depths 11241, 242 were 500 Å or less below the surface of the semiconductor substrate 11 (Figure (b)).

Next, CDE is performed to remove the polysilicon 1120, and the substrate 11 at the upper end of the grooves 121 and 122 is etched to round the edges, thereby forming the taper 12a.
~12d is formed ((C) figure).

Subsequently, etching is performed to remove the thermally oxidized film 19.
A CVD-3i02 film is again deposited and etched back to form trenches 12. , this CVD-8i only within 122
02 membrane 25. , 252, groove 1
2. , 122 are completely buried to form an element isolation region uL (FIG. 3(d)).

Next, a normal MOS FET formation process and wiring process are performed to form the gate insulating film 14. Gate electrode 15 and the like are formed to complete the semiconductor device.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a semiconductor device and its manufacturing method that can prevent the occurrence of the kink 11 phenomenon in subthreshold region characteristics and have stable device characteristics of 1q.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the invention, and FIG.
FIG. 4 is a diagram for explaining a conventional semiconductor device and its manufacturing method. FIG. 5 is a diagram showing gate voltage-channel current characteristics of the semiconductor device shown in FIG. 4. FIG. 3 is a diagram showing current characteristics. 11... semiconductor substrate, 12. , 122...groove, 1
2a to 12d...Taper, 131, 132...Insulating film (embedded element valve yl region), 241, 242
...First insulating film, 251°252... Second insulating film. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 4 Ehi ring 1 - Figure 5

Claims (2)

[Claims] (1) A semiconductor device in which an insulating film is embedded in a groove formed on the main surface of a semiconductor substrate to perform element isolation, characterized in that a taper is formed at the upper end of the groove in which the insulating film is embedded. Semiconductor equipment. (2) forming a groove on the main surface of the semiconductor substrate; burying a first insulating film in the groove to a predetermined depth; and isotropically etching the upper edge of the groove. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a taper by removing the groove; and filling the groove with a second insulating film up to the main surface of the semiconductor substrate.