JPS63298539A - Tracing device for program execution history - Google Patents

Abstract

PURPOSE:To facilitate investigation of the cause of generation of an infinite loop by setting in advance an instruction sequence of a known infinite loop to a first register group, shifting an instruction group which is read out in the course of executing a program, to a second register group, and collating the contents of both the register groups. CONSTITUTION:At the time of tracing a program execution history, when it is fallen into an infinite loop once, the instruction sequence of a one-cycle portion of this infinite loop can be known easily from the contents of a trace memory. Therefore, about the one-cycle portion of the known instruction sequence is set in advance to the first register groups 11a-11n. Also, while shifting an instruction group which is read out in the course of executing a program, to the second register groups 12a-12n which is cascaded, the contents of both the register groups are collated at every stage. In such a way, by detecting an appearance of the sequence of the infinite loop and inhibiting the trace, history information immediately before the generation of the infinite loop can be collected surely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a program execution history tracing device used for debugging during program development in the technical field of digital information processing.

Conventional technology In the field of digital information processing, when developing a program, the program to be tested is actually run, and the instructions read from memory as it runs are stored in trace memory in the order in which they were read. Therefore, trace devices that collect the execution history are widely used.

In such tracing devices, due to the storage capacity limit of the trace memory, when the contents of the trace memory become full, the collected history information is deleted from the oldest by overwriting the latest history information. It performs cyclical recording and sets operation interruption points called break points at appropriate locations.

The problem that the invention seeks to solve.

In the above-mentioned trace device that performs cyclic recording, if the program falls into an infinite loop due to an error in the program, the contents of the trace memory will be occupied by the history information of such an infinite loop. Therefore, there is a problem in that the history information before the occurrence of such an infinite loop, which is necessary for investigating the cause of the occurrence of the infinite loop, is completely erased.

If you try to set a breakpoint to avoid such a situation, setting it after the point where the infinite loop occurs is meaningless, and setting it a certain distance before the point makes it impossible to determine the cause of the occurrence. Therefore, it is necessary to set such a break point immediately before the point where the infinite loop occurs, and setting the break point requires a large number of trial and error processes, resulting in a time-consuming problem.

Means for solving the structural problems of the invention A program execution history tracing device according to the present invention has the following features:
a first group of registers holding a predetermined sequence consisting of a set of instructions in the program under test or their storage addresses on a storage device; A second group of cascade-connected registers that transfer and hold instructions in the order in which they are read; It includes a group of collation circuits that collates the contents held in each corresponding stage of the second group of registers, and a write prohibition means that prohibits writing to the trace memory when all of the collation circuits match. .

In other words, if a -H infinite loop occurs when tracing the program execution history, the instruction sequence for one cycle of this infinite loop can be easily known from the contents of the trace memory.

Therefore, approximately one cycle of this known instruction sequence is set in advance in the first register group, and while the instruction group read during program execution is shifted to the cascade-connected second register group, By comparing the contents of both register groups at each stage to detect the appearance of an infinite loop sequence and prohibit tracing, it becomes possible to reliably collect history information up to just before the infinite loop occurs.

Hereinafter, further details of the present invention will be explained together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a program history information tracing device according to an embodiment of the present invention, which is composed of a trace control section 10 and a trace memo IJ 20.

The trace control unit 10 includes n-stage collation instruction register groups 11a, 11b, llc...lln connected in cascade, and an n-stage execution instruction register group 12a also cascade-connected.
12b, 12(', ' 12n, and n matching circuits 13.a, 1 that match the contents of each stage of both register groups.
3b, 13cm・-13, and n. Furthermore, this trace control unit 10 includes matching circuits 133 to 13.
switches 14a, 14b, 14c, . . . , 14n that selectively fix the respective outputs of n to "1" or "0";
It includes an n-input AND gate 15 that receives the outputs of the collation circuits 13a to 13n at respective input terminals, and a counter 16 that counts the outputs of the AND gates.

If the change command output from the n-input AND gate 15 is low (0''), the trace memory 20 fetches the execution instruction output from the execution instruction register 12n.
Write in synchronization with the clock and increment the address. On the other hand, the trace memory 20 has an n-input AND gate 15
If the change command output from is high (“1”),
Counter 1 instead of the execution command of the above series of sequences
The number of matches output from 6 is written in a predetermined area, and the address is returned to its original value.

First, the program to be tested is run with the original function of the trace control unit 1.0 stopped.

This control function can be stopped by switching all the switches 14a to 14n of the trace control unit 10 to the signal line 17 side, fixing the logic state of the signal line 17 to low, and lowering the change command output from the AND gate 15. This is achieved by fixing the

When the test target program is run with this control function stopped, the instructions read from the program memory (not shown) are executed in the execution instruction register 1 in synchronization with the fetch clock.
23 to 12n, and is unconditionally written into the trace memory 20 as history information from the execution instruction register 12n at the final stage. When an infinite loop occurs as this program runs, trace memory 2
The contents of 0 are filled with just the repetition of this infinite loop sequence. The running of this program is forcibly terminated at an appropriate point, after which the contents of the trace memory 20 are read and the infinite loop sequence is determined.

Approximately one cycle of the infinite loop sequence found is synchronized with the shift pulse and is executed in the collation instruction register lla,
llb, llc, . . . , the switches 14a, 14b, 14c, . . . are switched to the output terminal side of the corresponding collation instruction register. Note that if the number of stages in this collation command register group is too large compared to the sequence length to be set, the corresponding switch is left switched to the signal line 17 side, and the signal line 17 is fixed at logic high. This disables part of the matching circuit and substantially reduces the number of matching stages.

When the setting of the sequence to the collation instruction register group 11a-11n is completed, the program starts running again, and the execution instructions read from the program memory are sent to the execution instruction registers 123-12 in synchronization with the fetch clock.
It is transferred within n. Until an infinite loop occurs,
Verification matches do not occur simultaneously in the valid verification circuit groups 13a to 13n, and therefore the output of the n-input AND gate 15 continues to maintain a low state. Along with this,
Execution instructions output from the instruction execution register 12n are sequentially written into the trace memory 20 in synchronization with the fetch clock.

After this, if an infinite loop occurs, the effective matching circuit 13
A match occurs in all of a, and the change command output from the n-input AND gate 15 rises high. This high output is also supplied to the counter 16 and is counted as - several times.

With the rise of the above change command, the execution command register 12n
Instead of the output of , the number of verifications counted by the counter 16 is written into a predetermined area of the trace memory 20.

Each time the above-mentioned predetermined sequence appears as the program runs, the operation of changing the write target as described above is repeated, and the new collation number incremented by the counter 16 is stored in the predetermined area of the trace memory 20. It has been updated with (.

When the count value reaches a predetermined value, the counter 16 overflows and is used as a break command to forcibly terminate the running of the program.

Note that for a normal loop in which a sequence similar to the infinite loop sequence is repeated a finite number of times, only the count value less than the overflow value of the counter 16 is verified.
It is recorded in the trace memory 20 as several times.

In the above example, when the sequences match, the number of times of matching is written in the trace memory instead of the execution command. However, it is also possible to simply prohibit writing of the execution command. In this case, the counting operation by the counter 16 and the generation of a break command due to its overflow may be omitted.

In addition, although we have illustrated a configuration in which an execution instruction read from a storage device as a program runs, a configuration in which the storage address of this execution instruction on a storage device is traced instead of or in addition to the execution instruction may also be used. Good too.

Furthermore, although a configuration has been illustrated in which corresponding register groups are connected in cascade in consideration of convenience in holding collation instruction groups, these register groups do not necessarily need to be cascaded.

Effects of the Invention As explained in detail above, the program execution history tracing device according to the present invention can eliminate almost one known infinite loop.
An instruction sequence for a cycle is set in advance in the first register group, and while the instruction group read during program execution is shifted to the cascade-connected second register group, the contents of both register groups are transferred to each register group. Since the system detects the appearance of an infinite loop sequence by checking each stage and prohibits tracing, it is possible to quickly and reliably collect history information up to the point immediately before the occurrence of an infinite loop, and to identify the cause of such an infinite loop. This has the effect of making it easier to investigate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a program execution history tracing device according to an embodiment of the present invention. 10...Trace control unit, lla to lln...First register group in which a sequence for approximately one cycle of a known infinite loop is set in advance, 12a to 12n... From the storage device when the program runs a second register group 13a- that transfers and holds the read execution instruction group;
13n... 1st. A group of collation circuits for collating the contents of the corresponding stage of the second group of registers, 15... n-input AND gate, 16... counter, 20... trace memory. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Scope of Claims] A trace memory; a first group of registers holding a predetermined sequence consisting of a set of instructions in a program to be tested or their storage addresses on a storage device; a cascade-connected second register group that transfers and holds instructions read from the storage device or their storage addresses in the order in which the instructions are read; and a second register group that stores the contents held in each corresponding stage of the first and second register groups. A program execution history tracing device comprising: a group of matching circuits for matching; and a write inhibiting means for prohibiting writing to the trace memory when all of the matching circuits match.