JPS63293927A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63293927A JPS63293927A JP62128178A JP12817887A JPS63293927A JP S63293927 A JPS63293927 A JP S63293927A JP 62128178 A JP62128178 A JP 62128178A JP 12817887 A JP12817887 A JP 12817887A JP S63293927 A JPS63293927 A JP S63293927A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- tin
- semiconductor element
- plated layer
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 239000008188 pellet Substances 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052737 gold Inorganic materials 0.000 abstract description 14
- 239000010931 gold Substances 0.000 abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 239000011889 copper foil Substances 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 238000009713 electroplating Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 230000005496 eutectics Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に係り、特に。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device.
テープリードを半導体素子の電極に接続する半導体装置
の製造方法に関する。The present invention relates to a method of manufacturing a semiconductor device in which tape leads are connected to electrodes of a semiconductor element.
従来のテープキャリヤ方式の半導体装置の製造方法にお
いては、ポリイミドフィルム上に銅箔をラミネートして
リードパターンを形成した後鍋めっきまたははんだめっ
きを行って作製したリードと、半導体素子電極上に形成
した金バンプとを。In the conventional tape carrier method for manufacturing semiconductor devices, a lead pattern is formed by laminating a copper foil on a polyimide film, and then a lead pattern is formed by pan plating or solder plating, and a lead pattern is formed on a semiconductor element electrode. With gold bumps.
ボンディングツールにより加熱圧着し、接続する方法が
とられていた。この種の製造方法の公知例としては、例
えば、特開間第５７−１０ｔ＄１５５号がある。The method used was to heat and press the parts using a bonding tool to connect them. A known example of this type of manufacturing method is, for example, Japanese Patent Application Laid-Open No. 57-10T$155.
しかしながら、従来の技術においては、上記錫またはは
んだのめつき層がリード表面全体を被覆する構成となっ
ているため、ボンディングツールによる加熱圧着の際に
、リードのツール側の面で溶融した錫あるいははんだが
ツール面に付着残留して、後続のボンディング時に片当
りを生ずることがあり、リードと素子上バンプとの接続
不良を生ずる原因となっていた。また、リード上の余分
な錫またははんだが素子上バンプの外側に流れ出て、素
子上に設けられた回路の電気的短絡を生ずる原因となる
問題があった。これらの問題点により、従来の製造方法
においては、ボンディングツールの清浄化、接続不良修
正あるいは短絡不良修正のための工数の増加を招いてい
た。However, in the conventional technology, the tin or solder plating layer is configured to cover the entire lead surface, so when the lead is hot-pressed using a bonding tool, molten tin or solder is formed on the tool side surface of the lead. Solder may remain attached to the tool surface, resulting in uneven contact during subsequent bonding, resulting in poor connection between the leads and the bumps on the element. Further, there is a problem in that excess tin or solder on the leads flows out to the outside of the bumps on the element, causing an electrical short circuit in the circuit provided on the element. Due to these problems, in the conventional manufacturing method, the number of man-hours for cleaning the bonding tool and correcting poor connections or short circuits increases.
本発明の目的は、従来の技術にみられる上記の欠点を取
り除き、信頼性の高い半導体装置の製造を可能にする有
効な製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an effective manufacturing method that eliminates the above-mentioned drawbacks found in the conventional technology and enables manufacturing of highly reliable semiconductor devices.
上記目的は、リード上の錫めっきあるいははんだめっき
の層をリードの半導体素子電極バンプ側の面上にのみ形
成すること、および、該めっき層の厚さを適量に制御す
ることにより達成される。The above object is achieved by forming a tin plating or solder plating layer on the lead only on the surface of the lead on the semiconductor element electrode bump side, and controlling the thickness of the plating layer to an appropriate amount.
リード上の錫めっきあるいははんだめっきの層をリード
の半導体素子電極バンブ側の面上にのみ形成することに
よって、加熱圧着時に、ボンディングツール面に錫ある
いははんだおよびそれらの酸化物が付着することがない
。従って、該ツール面は常に清浄に保たれており、ツー
ルの片当りによる接続不良の発生がな（なり、また、ツ
ールの清浄化工程も不要となる。By forming the tin plating or solder plating layer on the lead only on the surface of the lead on the semiconductor element electrode bump side, tin, solder, and their oxides will not adhere to the bonding tool surface during heat compression bonding. . Therefore, the tool surface is always kept clean, and connection failures due to uneven contact of the tool do not occur, and a tool cleaning process is also unnecessary.
また、リード面上の錫めっき層あるいははんだめっき層
の厚さを適量に制御することによって、加熱圧着時に、
余分な錫あるいははんだの流れ出しがなく、従って、従
来技術にみられた電気的短絡現象発生の可能性を防止す
ることができる。In addition, by appropriately controlling the thickness of the tin plating layer or solder plating layer on the lead surface, it is possible to
There is no excess tin or solder flowing out, thus preventing the possibility of electrical short circuits occurring in the prior art.
以下、本発明の一実施例を図により説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は、本発明の半導体装置の製造方法を説明するた
めのボンディング装置の全体断面図、第２図はその拡大
断面図を示す。ここで、半導体素子は、シリコン基板７
上に通常の工程で回路を形成し、さらに、電気めっき、
蒸着およびエツチングを利用する通常の方法によって電
極６上に金バンプ５を形成したものである。また、リー
ド５は、ポリイミドフィルム８上に銅箔をラミネートし
、゛さらに、ホトエツチング九よりリードパターンを形
成したもので、その半導体素子金バンプ５側の表面に厚
さ約０５μｍの錫めっき層４を設け、他面のボンディン
グツール１側の表面ば銅そのま１かあるいは酸化防止の
ために薄い金めつきを施したものである。FIG. 1 is an overall sectional view of a bonding apparatus for explaining the method of manufacturing a semiconductor device of the present invention, and FIG. 2 is an enlarged sectional view thereof. Here, the semiconductor element is a silicon substrate 7
A circuit is formed on top using the usual process, and then electroplating,
Gold bumps 5 are formed on electrodes 6 by a conventional method using vapor deposition and etching. The leads 5 are made by laminating copper foil on a polyimide film 8, and then forming a lead pattern by photo-etching, and a tin plating layer 4 with a thickness of about 0.5 μm is formed on the surface of the semiconductor element on the gold bump 5 side. The other surface on the side of the bonding tool 1 is made of pure copper or has a thin gold plating applied thereto to prevent oxidation.
ボンディングは、リード５を金バンプ５上に置いて位置
合わせをし、約５００〜６００℃の温度に保持したボン
ディングツールで押圧することにより、リード３上の錫
めっき層４を溶融し、金バンプ５とともに共晶組織を形
成させることによって行われる。The bonding is performed by placing the lead 5 on the gold bump 5, aligning it, and pressing it with a bonding tool kept at a temperature of approximately 500 to 600°C, thereby melting the tin plating layer 4 on the lead 3 and bonding the gold bump 5. This is done by forming a eutectic structure with 5.
以上述べた製造方法を適用することによって、ボンディ
ング時にボンディングツール１の面に錫およびその酸化
物が付着することがなく、また、余分な錫が金バンプ５
の外側に流れ出すことがないという結果が得られた。By applying the manufacturing method described above, tin and its oxides do not adhere to the surface of the bonding tool 1 during bonding, and excess tin is removed from the gold bumps 5.
The result was that there was no leakage to the outside.
また、上記リード上の錫めっき層の代りにはんだめっき
層を用いた場合にも、同様の結果が得られた。Similar results were also obtained when a solder plating layer was used instead of the tin plating layer on the lead.
以上述べてきたように、本発明の製造方法を適用するこ
とによって、ボンディング時にボンディングツール面に
錫あるいははんだおよびその酸化物の付着がないため、
ボンディングツールの清浄化が不要となり、工程数の短
縮が可能となる。また、ツール面の付着物によるボンデ
ィング時のツールの片当り現象がなくなるため、リード
と電極との接続不良の発生を低減し、ボンディング時の
歩留りを向上させることができる。さらに、余分な錫あ
るいははんだが金バンプの外側に流れ出すことがなく、
電気的短絡不良の発生を防ぎ、信頼性の高い接続を得る
ことができる。As described above, by applying the manufacturing method of the present invention, tin or solder and its oxides do not adhere to the bonding tool surface during bonding.
There is no need to clean the bonding tool, and the number of steps can be reduced. In addition, since the phenomenon of uneven contact of the tool during bonding due to deposits on the tool surface is eliminated, the occurrence of connection failures between leads and electrodes can be reduced, and the yield during bonding can be improved. Furthermore, excess tin or solder does not flow out of the gold bumps.
It is possible to prevent the occurrence of electrical short circuit defects and obtain highly reliable connections.
第１図は本発明の半導体装置の製造方法を説明するため
のボンディング装置の全体構成を示す断面図、第２図は
その拡大断面図である。
１・・・・・・ボンディングツール、２・・・・・・金
めつき層、６・・・・・・リード、４・・・・・・錫め
っき層、５・・・・・・金バンプ、６・・・・・・電極
、７・・・・・・シリコン基板、８・・・・・・ポリイ
ミドフィルム％ ９・・・・・・ステージ。FIG. 1 is a sectional view showing the overall structure of a bonding apparatus for explaining the method of manufacturing a semiconductor device of the present invention, and FIG. 2 is an enlarged sectional view thereof. 1... Bonding tool, 2... Gold plating layer, 6... Lead, 4... Tin plating layer, 5... Gold Bump, 6...electrode, 7...silicon substrate, 8...polyimide film% 9...stage.
Claims (1)
バンプに対応してテープリードを接続する工程を含む半
導体装置の製造方法において、半導体ペレットバンプ側
に面する表面のみに錫層またははんだ層を設けたテープ
リードを用いたことを特徴とする半導体装置の製造方法
。1. In a method for manufacturing a semiconductor device including a step of forming bumps on the electrodes of a semiconductor element pellet and connecting tape leads corresponding to each bump, a tin layer or a solder layer is formed only on the surface facing the semiconductor pellet bump side. 1. A method of manufacturing a semiconductor device, comprising using a tape lead provided with a tape lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128178A JPS63293927A (en) | 1987-05-27 | 1987-05-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128178A JPS63293927A (en) | 1987-05-27 | 1987-05-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63293927A true JPS63293927A (en) | 1988-11-30 |
Family
ID=14978347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62128178A Pending JPS63293927A (en) | 1987-05-27 | 1987-05-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63293927A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54163676A (en) * | 1978-06-15 | 1979-12-26 | Nippon Electric Co | Semiconductor device |
-
1987
- 1987-05-27 JP JP62128178A patent/JPS63293927A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54163676A (en) * | 1978-06-15 | 1979-12-26 | Nippon Electric Co | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333554B1 (en) | 1997-09-08 | 2001-12-25 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6344690B1 (en) | 1997-09-08 | 2002-02-05 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6495441B2 (en) | 1997-09-08 | 2002-12-17 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
| US6786385B1 (en) | 1997-09-08 | 2004-09-07 | Fujitsu Limited | Semiconductor device with gold bumps, and method and apparatus of producing the same |
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