JPS5925378B2 - How to mount electronic components - Google Patents

How to mount electronic components

Info

Publication number
JPS5925378B2
JPS5925378B2 JP6939680A JP6939680A JPS5925378B2 JP S5925378 B2 JPS5925378 B2 JP S5925378B2 JP 6939680 A JP6939680 A JP 6939680A JP 6939680 A JP6939680 A JP 6939680A JP S5925378 B2 JPS5925378 B2 JP S5925378B2
Authority
JP
Japan
Prior art keywords
conductor wiring
connection layer
pad
metal
electronic components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6939680A
Other languages
Japanese (ja)
Other versions
JPS56165333A (en
Inventor
一文 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6939680A priority Critical patent/JPS5925378B2/en
Publication of JPS56165333A publication Critical patent/JPS56165333A/en
Publication of JPS5925378B2 publication Critical patent/JPS5925378B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8122Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は電子部品特に、半導体素子の高密度実装方法に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to electronic components, and particularly to a method for high-density packaging of semiconductor devices.

従来、半導体装置の組立には、半導体素子上の電極(以
下パッドという)と外部電極を接続するのにワイヤボン
ディングを用いる方法あるいはワイヤボンディングを用
いずに直接外部リードに接続する方法がある。
Conventionally, semiconductor devices have been assembled by using wire bonding to connect electrodes on a semiconductor element (hereinafter referred to as pads) and external electrodes, or by connecting directly to external leads without using wire bonding.

ワイヤボンディングを用いる方法では、ボンディング装
置を用(゛一本一本行うため、高密度の組立が行えなか
つた。
The method using wire bonding does not allow for high-density assembly because bonding equipment is used (one wire at a time).

一方、ワイヤボンディングを用いな(゛方法として、本
発明に最も近いものにフリップチップ法がある。
On the other hand, as a method that does not use wire bonding, the flip-chip method is the closest to the present invention.

この方法では半導体素子側の電極表面に直接金属パンブ
を形成し、そのパンブを介して外部電極と接続する方法
である。すなわち、第1図に示すように、フリップチッ
プ法はあらかじめ半導体素子1のパッド表面に金属バン
プ2を形成しておき、この金属バンプ2と対向する外部
電極3の形成された耐熱性絶縁フィルム(以下、フィル
ムキャリアという)4を重ね合せて、前記金属バンプ2
を介して外部電極3と圧着接続する方法である。
In this method, a metal bump is formed directly on the surface of the electrode on the semiconductor element side, and the metal bump is connected to an external electrode via the bump. That is, as shown in FIG. 1, in the flip-chip method, metal bumps 2 are formed in advance on the pad surface of a semiconductor element 1, and a heat-resistant insulating film (on which external electrodes 3 are formed) facing the metal bumps 2 is formed. 4 (hereinafter referred to as a film carrier) are superimposed and the metal bumps 2
In this method, the external electrode 3 is connected to the external electrode 3 by pressure bonding.

なお、5は外部リードとして用(゛られろフィルムキャ
リア4上の導体配線、6は絶縁膜を示す。しかしながら
、従来のフリップチップ法の難点は、半導体素子上で直
接、種々の金属を蒸着メッキある(・はエッチング等の
処理によりバンプを形成するので 半導体素子の製造工
程が複雑になり、ほぼ完成された半導体素子に損傷を与
える場合がしばしばあつた。
Note that 5 is used as an external lead (conductor wiring on the film carrier 4, and 6 is an insulating film. However, the drawback of the conventional flip-chip method is that various metals are vapor-deposited and plated directly on the semiconductor element. Since the bumps are formed through processes such as etching, the manufacturing process for semiconductor devices becomes complicated, and almost completed semiconductor devices are often damaged.

また、通常半導体素子上へのバンプの形成には、バッチ
処理を行うのでバンプ形成工程で失敗するとほゞ完成さ
れた半導体素子がすべて不良となる。また、従来では1
個づつの半導体チップとの間隔をある程度とる必要があ
り、高密度の実装を行うことができなかつた。さらにま
た、以上の欠点を解決する方法として第2図に示す方法
が知られている。
Further, since bumps are usually formed on semiconductor devices by batch processing, if a failure occurs in the bump formation process, almost all of the completed semiconductor devices will be defective. Also, conventionally 1
It was necessary to provide a certain amount of space between each semiconductor chip, making it impossible to perform high-density packaging. Furthermore, a method shown in FIG. 2 is known as a method for solving the above-mentioned drawbacks.

すなわち、あらかじめガラス基板11上に導体配線12
を形成しておき、さらにこの導体配線上で、半導体素子
13上の電極パッド14に対応する部分には、低融点ガ
ラス層15が形成されている。
That is, the conductor wiring 12 is placed on the glass substrate 11 in advance.
A low melting point glass layer 15 is further formed on the conductor wiring at a portion corresponding to the electrode pad 14 on the semiconductor element 13.

(第2図a)次に、この低融点金属層15を介して半導
体素子13のパツド14と、前記導体配線を位置合せし
て密着する(第2図b)。
(FIG. 2a) Next, the pad 14 of the semiconductor element 13 and the conductor wiring are aligned and brought into close contact with each other via this low melting point metal layer 15 (FIG. 2b).

その後、ガラス基板11側より、順次レンズ等にて集光
した光線Aを照射し、前記導体配線12のパツド14に
対向した部分を昇温して、局所的に低融点金属層15を
15゛のごとく溶融し、導体配線22とパツド25を接
続する(第2図c)。
Thereafter, from the glass substrate 11 side, a light beam A focused by a lens or the like is sequentially irradiated to raise the temperature of the portion of the conductor wiring 12 facing the pad 14, thereby locally heating the low melting point metal layer 15 by 15°. The conductor wiring 22 and the pad 25 are then melted as shown in FIG. 2c.

しかしながら、この方法では、レーザー照射による加熱
を行う際、位置合せズレが生じな(゛ように固定してお
く必要がある。一方、低融点金属と導体配線の濡れ性を
良くするため、導体配線およびパツド表面は金メツキ等
の耐酸化性金属で被つておく必要がある。さらにまた、
レーザー照射時に低融点金属が酸化するのを防止するた
め、雰囲気を不活性ガスとするか、真空中で行う必要が
あつた。以上述べてきた欠点に鑑み、本発明の目的は半
導体素子等の電子部品および外部導体配線の電極に何ら
特殊な加工を施すことなくワィヤレスボンデイングが容
易に行なえ、しかも高密度実装が行なえることを特徴と
した電子部品の実装方法を提供することにある。
However, with this method, when heating by laser irradiation, it is necessary to fix the position so that it does not misalign.On the other hand, in order to improve the wettability of the low melting point metal and the conductor wiring The pad surface must be covered with oxidation-resistant metal such as gold plating.Furthermore,
In order to prevent the low melting point metal from oxidizing during laser irradiation, it was necessary to use an inert gas atmosphere or to perform the process in vacuum. In view of the above-mentioned drawbacks, an object of the present invention is to easily perform wireless bonding without performing any special processing on electronic components such as semiconductor elements and electrodes of external conductor wiring, and to enable high-density mounting. An object of the present invention is to provide a method for mounting electronic components characterized by the following.

次に、本発明の一実施例を、第3図とともに説明する。Next, one embodiment of the present invention will be described with reference to FIG.

第3図〜第5図にお(゛て、第2図と同じものには同一
番号を付して示す。第3図a−dにおいてまず、膨張係
数が半導体素子に近いガラス基板11(例えばパィレツ
クスガラス(コーニング社商標)やサファイアのような
透明基板)上に、導体薄膜を形成(例えば銅を1〜2μ
mの厚みで蒸着)し、通常のIC製造技術であるホトリ
ソ法を用いて、導体配線12を形欣する(第3図a)。
In FIGS. 3 to 5, the same parts as in FIG. 2 are denoted by the same numbers. In FIGS. A conductive thin film is formed on a transparent substrate such as Pyrex glass (trademark of Corning Co., Ltd.) or sapphire (for example, copper of 1 to 2 μm
The conductor wiring 12 is formed using photolithography, which is a common IC manufacturing technique (FIG. 3a).

次に、粘着性を有する有機物質と金属微粉末を混合して
なるペースト(接続層と(・う)25(例えば、半田ペ
ーストを50〜100μm程度の厚みで)を全面に塗布
し、この接続層25を介して半導体素子13のパッド1
4と、前記導体配線12とを位置合せし、接続層の粘着
性を利用して貼り付ける(第3図b)。
Next, a paste (connection layer) 25 (for example, solder paste with a thickness of about 50 to 100 μm) made of a mixture of an adhesive organic substance and a fine metal powder is applied to the entire surface, and the connection layer is Pad 1 of semiconductor element 13 via layer 25
4 and the conductive wiring 12 are aligned and pasted using the adhesiveness of the connection layer (FIG. 3b).

その後、ガラス基板12側より、順次たとえばレンズに
て集光した光線A(例えば、基板がガラスであればYA
Gレーザで基板がSiであればCO2レーザーでパツド
面積よりやや大きく集光したもの)を照射し、前記導体
配線12のパツド14に対向した部分を昇温し、局所的
に接続層25を溶融さらに、金属粉末25Iを溶融析出
させ、導体配線12とそれに対応するパッド14を接続
する。
After that, from the glass substrate 12 side, light rays A (for example, if the substrate is glass, YA
If the substrate is made of Si, a G laser is used to irradiate a CO2 laser (focused slightly larger than the pad area) to raise the temperature of the portion of the conductor wiring 12 facing the pad 14, and locally melt the connection layer 25. Further, metal powder 25I is melted and precipitated to connect the conductor wiring 12 and the corresponding pad 14.

このとき、導体配線とパンドのギャツプが埋められる(
第3図c)。このとき、接続中に含まれる金属は、導体
配線12およびパツド14の金属よりも融点の低いもの
を用いる必要がある。例えば導体配線お びパツド表面
を銅で形成しておき、接続層として半田粉末をフラツク
スに混入したペーストを用いれば、レーザビームを用い
局所的に200〜300℃に加熱することにより、導体
配線とパツドの間に半田を析出させて、導通を得ること
ができた。なお、以上の方法はパツドのみ局所加熱を行
うので、ボンデイング時にチツプの位置合せがズレルこ
ともない。すなわちチツプの仮固定はフラツクスの粘着
性で十分であつた。最後に、接続層25の未溶融部分2
51を有機溶剤等で洗浄除去し、半導体素子と導体配線
の接続を完了する(第3図d)。
At this time, the gap between the conductor wiring and the pad is filled (
Figure 3c). At this time, the metal included in the connection must have a melting point lower than that of the metal of the conductor wiring 12 and pad 14. For example, if the conductor wiring and pad surfaces are made of copper and a paste containing solder powder mixed in flux is used as the connection layer, the conductor wiring and pad surfaces can be connected by heating locally to 200 to 300°C using a laser beam. By depositing solder between the pads, we were able to obtain continuity. In addition, since the above method locally heats only the pad, there is no misalignment of the chip during bonding. In other words, the adhesiveness of the flux was sufficient for temporarily fixing the chip. Finally, the unmelted portion 2 of the connection layer 25
51 is removed by washing with an organic solvent or the like, and the connection between the semiconductor element and the conductor wiring is completed (FIG. 3d).

このとき、接続層の洗浄除去を容易に行うためには、透
明基板側の導体配線の無い部分に、第4図のごと〈貫通
穴26あるいは溝27を設けておけば良い。なお、本発
明の実施例において接続層25として半田ペーストを用
いる場合には、半導体素子の仮固定、レーザー加熱時の
電極パツド部あるいは導体配線部の酸化防止および溶出
金属のぬれ性の改善等が同時にはかれて都合が良い。
At this time, in order to easily clean and remove the connection layer, it is sufficient to provide a through hole 26 or groove 27 (as shown in FIG. 4) in a portion of the transparent substrate where there is no conductor wiring. In addition, when a solder paste is used as the connection layer 25 in the embodiment of the present invention, it can temporarily fix the semiconductor element, prevent oxidation of the electrode pad part or conductor wiring part during laser heating, and improve the wettability of eluted metal. It is convenient to wear them at the same time.

また、導体配線として非常に反射率の高い金属例えばA
t等を用いた場合には、基板ガラスと導体配線の間に、
光の吸収層を設けておけば、光のエネルギーを有効に利
用できる。
In addition, metals with very high reflectivity such as A
When using t etc., between the substrate glass and the conductor wiring,
By providing a light absorption layer, the energy of light can be used effectively.

以上の方法を用いれば、半導体素子側あるいは導体配線
の形成された基板側に特別な処理を施すことなく、ワイ
ヤレスボンデイングが行なえるので、非常に歩留が良く
、しかも製造コストの非常に安い半導体素子の組立が行
なえる。
By using the above method, wireless bonding can be performed without special processing on the semiconductor element side or the substrate side on which conductor wiring is formed, resulting in a very high yield and a very low manufacturing cost for semiconductors. Devices can be assembled.

また、半導体素子と導体配線の接続は、対向面でのみ局
所加熱を行うので、接続層の粘殖性による仮固定でも加
熱中チツプの位置がズレルことがなく複数個の半導体素
子を同時に実装する場合、究極的には半導体素子間のギ
ヤツプをほとんど取る心配がなく、さらに・ガラス基板
上に多層の導体配線も形成することができるので、第5
図のごとく、多数の半導体素子の非常に高密度の実装を
たとえば数十ミクロン程度の間隔で行うことができると
ともに、透明基板上に多層の導体配線を形成してより一
層高密度化を可能とすることができる。さらにまた、本
実施例では導体配線12上に接続層25を形成した例を
示したが、反対に、パッド14上にのみ形成した場合で
も同じ効果が得られることは明らかである。
In addition, since local heating is performed only on the opposing surfaces to connect the semiconductor element and the conductor wiring, the position of the chip will not shift during heating even if it is temporarily fixed due to the viscosity of the connection layer, making it possible to mount multiple semiconductor elements at the same time. In this case, there is ultimately no need to worry about creating gaps between semiconductor elements, and furthermore, multilayer conductor wiring can be formed on the glass substrate, so the fifth
As shown in the figure, it is possible to implement extremely high-density packaging of a large number of semiconductor elements at intervals of, for example, several tens of microns, and it is also possible to form multilayer conductor wiring on a transparent substrate to achieve even higher density. can do. Furthermore, although this embodiment shows an example in which the connection layer 25 is formed on the conductor wiring 12, it is clear that the same effect can be obtained even when the connection layer 25 is formed only on the pad 14.

なお、本発明は、半導体素子の組立特に高密度実装に非
常に有用な方法であるが、半導体素子以外の電子部品に
も適応す一ることができる。
Although the present invention is a very useful method for assembling semiconductor devices, particularly for high-density packaging, it can also be applied to electronic components other than semiconductor devices.

従つて、本発明は電子部品の容易かつ高密度な実装に大
きく寄与するものである
Therefore, the present invention greatly contributes to easy and high-density mounting of electronic components.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフイルムキヤリヤと金属バンプの形成さ
れた半導体素子の断面図、第2図a−cは本発明のバン
プレス・ワイヤレスボンデイング法の工程断面図、第3
図a−dは本発明の他の実施例のワイヤレスボンデイン
グ法の工程断面図、第4図は本発明の方法にかかる他の
透明基板を用いた半導体素子の組立断面図を示す。 11・・・ガラス基板、12・・・導体配線、13・・
・半導体基板、14・・・パッド、15・・・低融点金
属層、25・・・半田ペースト。
FIG. 1 is a cross-sectional view of a conventional film carrier and a semiconductor element on which metal bumps are formed, FIGS. 2 a-c are process cross-sectional views of the bumpless wireless bonding method of the present invention, and
Figures a to d are cross-sectional views showing the steps of a wireless bonding method according to another embodiment of the present invention, and Fig. 4 is a cross-sectional view showing the assembly of a semiconductor device using another transparent substrate according to the method of the present invention. 11... Glass substrate, 12... Conductor wiring, 13...
- Semiconductor substrate, 14... Pad, 15... Low melting point metal layer, 25... Solder paste.

Claims (1)

【特許請求の範囲】 1 透明基板上に形成された導体配線と電子部品上に形
成された接続用パッドを、有機物質と金属微粉末を混合
してなるペースト状の接続層を介し位置合せ仮接着し、
さらに前記接続層を集合した光で照射することにより局
所的に昇温し、前記接続層中の金属微粉末を極所的に溶
融したのち、前記接続層の未溶融部分を洗浄除去して前
記導体配線とパッドとの電気的接続を行うことを特徴と
する電子部品の実装方法。 2 接続層中の金属微粉末が半田等の低融点合金よりな
ることを特徴とする特許請求の範囲第1項に記載の電子
部品の実装方法。 3 接続層が導体配線または接続用パッドの少くとも一
方のパッド対応部にのみ塗布されていることを特徴とし
た特許請求の範囲第1項に記載の電子部品の実装方法。
[Claims] 1. Conductor wiring formed on a transparent substrate and connection pads formed on an electronic component are temporarily aligned through a paste-like connection layer made of a mixture of an organic substance and fine metal powder. Glue and
Furthermore, the connection layer is irradiated with concentrated light to locally raise the temperature, locally melting the metal fine powder in the connection layer, and then washing and removing the unmelted portion of the connection layer. A method for mounting electronic components, characterized by electrically connecting conductor wiring and pads. 2. The electronic component mounting method according to claim 1, wherein the metal fine powder in the connection layer is made of a low melting point alloy such as solder. 3. The electronic component mounting method according to claim 1, wherein the connection layer is applied only to a corresponding portion of at least one of the conductor wiring or the connection pad.
JP6939680A 1980-05-23 1980-05-23 How to mount electronic components Expired JPS5925378B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6939680A JPS5925378B2 (en) 1980-05-23 1980-05-23 How to mount electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6939680A JPS5925378B2 (en) 1980-05-23 1980-05-23 How to mount electronic components

Publications (2)

Publication Number Publication Date
JPS56165333A JPS56165333A (en) 1981-12-18
JPS5925378B2 true JPS5925378B2 (en) 1984-06-16

Family

ID=13401395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6939680A Expired JPS5925378B2 (en) 1980-05-23 1980-05-23 How to mount electronic components

Country Status (1)

Country Link
JP (1) JPS5925378B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188995A (en) * 1983-04-11 1984-10-26 沖電気工業株式会社 Method of solder connecting and inspecting electronic part and circuit board
JP2545899B2 (en) * 1987-12-17 1996-10-23 ソニー株式会社 Solid-state imaging device and manufacturing method thereof
US4893742A (en) * 1988-12-21 1990-01-16 Hughes Aircraft Company Ultrasonic laser soldering
JPH0429338A (en) * 1990-05-24 1992-01-31 Nippon Mektron Ltd Method circuit board for mounting ic and its mounting
JP2006303357A (en) * 2005-04-25 2006-11-02 Ricoh Microelectronics Co Ltd Packaging method of electronic component
DE102009017659A1 (en) * 2009-04-16 2010-10-28 Schott Ag Method for the conductive connection of a component on a transparent substrate

Also Published As

Publication number Publication date
JPS56165333A (en) 1981-12-18

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